Nanotechnology Now - Press Release: Cadence Extends Performance Leadership With Expanded Multi-Core Support: Enhanced Engine Performance in Design, Verification, Custom, PCB and IC Packaging Broadens Cadence Multi-Core Support

Home > Press > Cadence Extends Performance Leadership With Expanded Multi-Core Support: Enhanced Engine Performance in Design, Verification, Custom, PCB and IC Packaging Broadens Cadence Multi-Core Support

Abstract:
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced the immediate availability of dramatically expanded support for multi-core processors across multiple technology domains. These new capabilities significantly improve performance and throughput of key products in the Cadence® Encounter® digital IC design, Incisive® verification, Virtuoso® custom IC, and Allegro® PCB and IC packaging platforms. These improvements represent the latest in Cadence's ongoing initiatives to address the changing landscape of computing infrastructure by providing leading multi-core support for a wide range of products across all segments of the EDA industry.

Cadence Extends Performance Leadership With Expanded Multi-Core Support: Enhanced Engine Performance in Design, Verification, Custom, PCB and IC Packaging Broadens Cadence Multi-Core Support

San Jose, CA | Posted on September 29th, 2009

New multi-core capabilities within Encounter include support in the Conformal product family. Encounter Conformal Equivalence Checker automatically partitions designs to speed up the comparison across multiple cores, checking for equivalence of each portion and then combining the results. It also utilizes concurrent algorithms to verify more complex circuits.

The Incisive Enterprise Simulator family has added the first stage of multi-core support, allowing parallelization of the simulation process. In addition, Incisive Formal Verifier now provides support for the distribution of formal engines across multiple cores, with automatic selection based upon design size and complexity.

"We have experienced performance improvements of up to 2X with the initial multi-core capability in IES," said YJ Patil, manager of Video IP IC Verification Engineering, TV and Monitor Division, Home Entertainment and Displays, at STMicroelectronics. "The approach used by Cadence is independent of design style, so we expect all of our projects to benefit from current and future enhancements."

Virtuoso Analog Design Environment (ADE) now provides multi-core distributed processor capabilities. ADE XL provides automatic partitioning and distribution of multi-test, multi-corner and Monte Carlo simulations for performance improvement of two to five times. ADE GXL now offers multi-core circuit optimization with speedup of 1.5 to three times, and parametric yield optimization with speedup of 1.5 to five times. These performance-related improvements enable designs to be simulated and optimized in parallel across multiple environmental and process variations while verifying the combined results against design specifications. Virtuoso MMSIM also now includes multi-core capabilities, allowing its SPICE circuit simulations to scale across multiple processors for increased performance.

Finally, the Allegro platform will provide multi-core support for design rule checking for its PCB, IC packaging and SiP implementation technologies in Q4 of 2009. This support has demonstrated performance increases of up to three times when using a quad-core processor.

"The computing paradigm started changing from scalar to multi-core architectures years ago, and we fully embraced that trend," said Charlie Giorgetti, corporate vice president of Solutions and Product Marketing at Cadence. "By expanding our pioneering support for multi-core processors, we are continuing our long tradition of technology and solution leadership, helping our customers to do designs more efficiently, and with less risk."

The new multi-core capabilities complement the extensive multi-core support already available across a wide range of product lines at Cadence. These products include Encounter RTL Compiler; Encounter Digital Implementation System; Encounter Timing System; Encounter Power System; Cadence QRC Extraction; Virtuoso Accelerated Parallel Simulator; Cadence Physical Verification System; Assura Physical Verification; the Cadence DFM suite, including Litho Physical Analyzer, Litho Electrical Analyzer, and CMP Predictor; Incisive Verifault-XL; and the Incisive Palladium series of accelerators/emulators.

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About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, Allegro, Encounter, Incisive, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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Contacts:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226

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