Home > News > NEC says 55-nm process cuts power consumption
December 6th, 2005
NEC says 55-nm process cuts power consumption
Abstract:
Japan-based NEC Electronics Corp. announced Monday (Dec. 5) that it has developed a 55-nm node process named UX7LS that will employ emersion lithography and higher dielectric constant (high-k) material. The company claims the process provides one-tenth lower power consumption in both operating and standby modes, than 65nm processes.
Source:
EETimes
Bookmark:
| Related News Press |
Chip Technology
A reusable chip for particulate matter sensing April 17th, 2026
Metasurfaces smooth light to boost magnetic sensing precision January 30th, 2026
Nanoelectronics
Lab to industry: InSe wafer-scale breakthrough for future electronics August 8th, 2025
Interdisciplinary: Rice team tackles the future of semiconductors Multiferroics could be the key to ultralow-energy computing October 6th, 2023
Key element for a scalable quantum computer: Physicists from Forschungszentrum Jülich and RWTH Aachen University demonstrate electron transport on a quantum chip September 23rd, 2022
Reduced power consumption in semiconductor devices September 23rd, 2022
Announcements
A fundamentally new therapeutic approach to cystic fibrosis: Nanobody repairs cellular defect April 17th, 2026
UC Irvine physicists discover method to reverse ‘quantum scrambling’ : The work addresses the problem of information loss in quantum computing system April 17th, 2026
 |
||
 |
||
| The latest news from around the world, FREE | ||
 |
||
|
|
||
| Premium Products | ||
 |
||
|
Only the news you want to read!
Learn More |
||
 |
||
|
Full-service, expert consulting
Learn More |
||
|
|
||