Nanotechnology Now

Our NanoNews Digest Sponsors
Heifer International



Home > News > Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

May 26th, 2004

Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

Abstract:
STMicroelectronics today announced that ST, CEA-Leti and AIXTRON have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes. The new process significantly reduces transistor leakage current by the deposition of 'high-k' gate-insulation material.

Source:
Businesswire

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

Chip Technology

Unconventional superconductor acts the part of a promising quantum computing platform: If it looks like a duck, swims like a duck and quacks like a duck, then it probably is a duck. July 16th, 2021

Repairs using light signals: FAU research group develops smart microparticle that identifies defective parts in electrical appliances July 16th, 2021

Scientists take first snapshots of ultrafast switching in a quantum electronic device: They discover a short-lived state that could lead to faster and more energy-efficient computing devices July 16th, 2021

Stress-free path to stress-free metallic films paves the way for next-gen circuitry: Optimized sputtering technique helps minimize stress in tungsten thin films July 4th, 2021

NanoNews-Digest
The latest news from around the world, FREE




  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More











ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project