- About Us
- Nano-Social Network
- Nano Consulting
- My Account
Key processes critical for building a strong infrastructure for volume production of TSVs
Researchers from SEMATECH's 3D Interconnect program based at the College of Nanoscale Science and Engineering's (CNSE) Albany NanoTech Complex have reported advances in wafer-to-wafer bonding alignment accuracies through a series of tool and process hardening improvements. At the same time, the SEMATECH team has explored unique 3D metrology and failure analysis techniques to complement bonding tool development. These results are key steps towards bridging high-volume manufacturing readiness gaps for an integrated bonding tool platform and developing metrology techniques that will accelerate adoption of 3D integration technology. SEMATECH presented the results at the 2010 IEEE International Interconnect Technology Conference (IITC) on Wednesday, June 9, in Burlingame, CA.
Wafer-to-wafer (WtW) alignment and bonding are key enabling process steps for 3D interconnection of wafers through stacking. The International Technology Roadmap for Semiconductors (ITRS) roadmap for high density, intermediate level, through-silicon-vias with WtW bonding specifies via diameters of 0.8 to 1.5ìm in 2012 and beyond. Post bond overlay accuracy of 0.5 to 1.0ìm is necessary for these devices.
SEMATECH's 3D interconnect researchers have demonstrated submicron alignment accuracies for copper-to-copper (Cu-Cu) thermo-compression bonds and a variety of silicon-to-silicon and oxide-to-oxide fusion bonds without sacrificing bonding uniformity and bonding strength, using an integrated 300mm WtW pre-processing, aligning, and bonding tool. Additionally, to enhance process control, related metrology development on bonding interface defectivity and overlay metrology were reported. SEMATECH's latest achievements are promising indications of the feasibility of meeting the WtW bonding roadmap as outlined in the ITRS.
"Through collaborative research, our goal is to develop and characterize new approaches to implementing 3D," said Sitaram Arkalgud, director of SEMATECH's 3D Interconnect Program. "These leading-edge results, which have a direct impact on processing costs, demonstrate SEMATECH's leadership and innovative techniques that pave the way for low-cost 3D IC integration."
With the rising demand for smaller, more functional and lower-power chips, 3D architecture is emerging as a leading solution for meeting leading-edge consumer device requirements. SEMATECH's 3D program was established at CNSE's Albany NanoTech Complex to deliver robust 300 mm equipment and process technology solutions for high-volume through-silicon via (TSV) manufacturing. To accelerate progress in realizing 3D's potential as a manufacturable and affordable technology for memory and CMOS manufacturers, the program's engineers have been working jointly with chipmakers, equipment and materials suppliers, and assembly and packaging service companies from around the world on early development challenges, including cost modeling, technology option narrowing, and technology development and benchmarking.
For over 20 years, SEMATECH® (www.sematech.org), the international consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.
The UAlbany CNSE is the first college in the world dedicated to education, research, development, and deployment in the emerging disciplines of nanoscience, nanoengineering, nanobioscience, and nanoeconomics. CNSE’s Albany NanoTech Complex is the most advanced research enterprise of its kind at any university in the world. With over $5.5 billion in high-tech investments, the 800,000-square-foot complex attracts corporate partners from around the world and offers students a one-of-a-kind academic experience. The UAlbany NanoCollege houses the only fully-integrated, 300mm wafer, computer chip pilot prototyping and demonstration line within 80,000 square feet of Class 1 capable cleanrooms. More than 2,500 scientists, researchers, engineers, students, and faculty work on site at CNSE’s Albany NanoTech, from companies including IBM, AMD, GlobalFoundries, SEMATECH, Toshiba, Applied Materials, Tokyo Electron, ASML, Novellus Systems, Vistec Lithography and Atotech. For more information, visit www.cnse.albany.edu.
For more information, please click here
SEMATECH | Media Relations
257 Fuller Road | Suite 2200 | Albany, NY | 12203
o: 518-649-1041 | m: 518-487-8256
Copyright © SEMATECHIf you have a comment, please Contact us.
Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.
|Related News Press|
News and information
SUNY Polytechnic Institute Announces Total of 172 Teams Selected to Compete in Solar in Your Community Challenge: Teams from 40 states, plus Washington, DC, 2 Territories, and 4 American Indian Reservations, Will Deploy Solar in Underserved Communities April 20th, 2017
UC researchers use gold coating to control luminescence of nanowires: University of Cincinnati physicists manipulate nanowire semiconductors in pursuit of making electronics smaller, faster and cheaper March 17th, 2017
National Conference on Nanomaterials, (NCN-2017) April 21st, 2017
Nanomechanics, Inc. Unveils New Product at ICMCTF Show April 25th: Nanoindentation experts will launch the new Gemini that measures the interaction of two objects that are sliding across each other – not merely making contact April 21st, 2017
Forge Nano 2017: 1st Quarter Media Update April 20th, 2017
Better living through pressure: Functional nanomaterials made easy April 19th, 2017
Shedding light on the absorption of light by titanium dioxide April 14th, 2017