Home > News > Nanometer ICs have stringent testing requirements
October 25th, 2006
Nanometer ICs have stringent testing requirements
Abstract:
As the EDA industry focuses on design-for-manufacturability (DFM), the older problem of design-for-test has almost been forgotten. But ICs built at 90 nanometers and below pose new and troubling challenges for DFT tools and techniques, according to providers who will take part in this week's International Test Conference here.
Source:
EETimes
Bookmark:
| Related News Press |
Nanoelectronics
Lab to industry: InSe wafer-scale breakthrough for future electronics August 8th, 2025
Interdisciplinary: Rice team tackles the future of semiconductors Multiferroics could be the key to ultralow-energy computing October 6th, 2023
Key element for a scalable quantum computer: Physicists from Forschungszentrum Jülich and RWTH Aachen University demonstrate electron transport on a quantum chip September 23rd, 2022
Reduced power consumption in semiconductor devices September 23rd, 2022
Announcements
Decoding hydrogen‑bond network of electrolyte for cryogenic durable aqueous zinc‑ion batteries January 30th, 2026
COF scaffold membrane with gate‑lane nanostructure for efficient Li+/Mg2+ separation January 30th, 2026
 |
||
 |
||
| The latest news from around the world, FREE | ||
 |
||
|
|
||
| Premium Products | ||
 |
||
|
Only the news you want to read!
Learn More |
||
 |
||
|
Full-service, expert consulting
Learn More |
||
|
|
||