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|Artist’ concept of 3D silicon processor chip with optical IO layer featuring on-chip nanophotonic network. Courtesy IBM.|
Development of on-chip optical interconnects for future multi-core processors
The ultimate goal of this project is to develop a technology for on-chip integration of ultra-compact nanophotonic circuits for manipulating the light signals, similar to the way electrical signals are manipulated in computer chips. Nanoscale silicon photonics circuits are being developed to enable the integration of complete optical systems on a monolithic semiconductor chip that would eventually allow to overcome severe constraints of today's mostly copper I/O interconnects.
The current tendency in high performance computing systems is to increase the parallelism in processing at all levels utilizing multithreads, increasing the number of chips in racks and blades, as well as increasing the number of cores on a chip. The scaling of overall system performance that soon might approach Exaflop/s is, however, out of balance with respect to limited available bandwidth for shuttling ExaBytes of data across the system, between the racks, chips and cores.
Optics is destined to be utilized in data centers since optical communications can meet the large bandwidth demands of high-performance computing systems by bringing the immense advantages of high modulation rates and parallelism of wavelength division multiplexing. As it already happened in long-haul communications decades ago when optical fibers replaced copper cables, the copper cables that connect racks in the datacenters are started now to being replaced by optical fibers. Following the same trend optics can become competitive with copper at shorter and shorter distances eventually leading to optical on-board and may be even on-chip communications.
This future 3D-integated chip consists of several layers connected with each other with very dense and small pitch interlayer vias. The lower layer is a processor itself with many hundreds of individual cores. Memory layer (or layers) are bonded on top to provide fast access to local caches. On top of the stack is the Photonic layer with many thousands of individual optical devices (modulators, detectors, switches) as well as analogue electrical circuits (amplifiers, drivers, latches, etc.). The key role of a photonic layer is not only to provide point-to-point broad bandwidth optical link between different cores and/or the off-chip traffic, but also to route this traffic with an array of nanophotonic switches. Hence it is named Intra-chip optical network (ICON).
Silicon photonics offers high density integration of individual optical components on a single chip. Strong light confinement enables dramatic scaling of the device area and allows unprecedented control over optical signals. Silicon nanophotonic devices have immense capacity for low-loss, high-bandwidth data processing. Fabrication of silicon photonics system in the complementary metal-oxide-semiconductor (CMOS)-compatible silicon-on-insulator platform also results in further integration of optical and electrical circuitry. Following the Moore's scaling laws in electronics, dense chip-scale integration of optical components can bring the price and power per a bit of transferred data low enough to enable optical communications in high performance computing systems.
To meet these stringent requirements and utilize fully all the benefits of optics an innovative engineering is necessary at all levels starting from the design of individual devices to the overall architecture of high-performance computing system. Nanoscale silicon photonics circuits that are being developed within this project are targeted to enable the monolithic integration of complete optical systems on a semiconductor chip.
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