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Home > Press > Intel teams up with Glasgow University to facilitate the design of future nanoscale memories

Abstract:
A European taskforce has been set up to investigate how to design the next generation of tera-scale computer memory systems.

Intel teams up with Glasgow University to facilitate the design of future nanoscale memories

EU | Posted on February 22nd, 2010

Within the next decade microchips are expected to incorporate billions of transistors - the tiny on-off switches that enable circuits to process and store data - creating ultra-powerful computer systems that can process trillions of bytes (terabytes) of data per second.

However, as transistors get smaller, so tiny variations within their structures affect their performance and thus the reliability of the whole microchip. It is a problem which presents a huge barrier to the continued scaling of microchips and the development of ever-more powerful computers.

In order to overcome this obstacle the European Commission (EC) has established a taskforce to come up with new ways of designing future microchip memories which take into account the variability and unreliability of nano-scale transistors.

The 'Tera-scale Reliable Adaptive Memory Systems' (TRAMS) consortium includes: Intel Corporation Iberia, Interuniversitair Micro-Elektronica Centrium vzw, the University of Glasgow, and the Universitat Politecnica de Catalunya, and is financed through the EU's Framework Programme 7 (FP7) science research fund.

Professor Asen Asenov, of the Department of Electronic and Electrical Engineering is leading the University of Glasgow's involvement at the heart of the project. He is a world-leading authority on the variability of Complementary Metal-Oxide Semiconductors (CMOS) transistors and microchips.

He said: "Tera-scale computing will transform the power, performance and functionality of personal computers, phones and other electronic devices as well as large computing facilities such as data centres. "However, if we are to continue to shrink the size of transistors in order to develop such powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the variability within transistors.

"We hope this project will result in new chip design paradigms for building reliable memory systems out of unreliable nano-scale components cheaply and effectively, heralding the era of tera-scale computing." Central to the project is simulation software developed by Prof Asenov in an earlier GBP5.3m Engineering and Physical Sciences Research Council eScience pilot project called NanoCMOS.

The NanoCMOS simulations use grid computing, which utilises the processor power of thousands of linked computers, to simulate how hundreds of thousands of transistors, each with their own individual characterstics, will function within a circuit.

Prof Asenov and the University of Glasgow is setting up a company called Gold Standard Simulations to exploit this technology which will be critical to the work of the TRAMS project, with all device design and simulation work being conducted at Glasgow.

In investigating design possibilities for future microchips, the team will focus on future generation of CMOS microchip technologies - which comprise transistors less than 16 nanometres in size (by comparison a human hair is around 100,000 nanometres wide). The transistors will be design and simulated exclusively by Glasgow.

The TRAMS consortium will also consider what are known as 'Beyond CMOS' technologies; nanowire transistors, quantum devices, carbon nanotubes and molecular electronics, which are expected to be as small as five nanometres.

The project is expected to last three years.

Notes: The Universitat Politecnica de Catalunya (UPC), Barcelona Tech, the Spanish technical university located in Barcelona is the project coordinator. The UPC is one of the main technical universities in Spain. It is specialized in the areas of engineering, science and architecture. It has around 30,000 undergraduate students and 4,000 graduate students (Master and Doctorate). The UPC participation in the TRAMS project is through the research groups "High Performance Integrated Circuits and Systems Design" (HIPICS) and "Architecture and Compilers" (ARCO) in the Electronics Engineering and Computer Architecture Departments respectively.

The University of Glasgow (UOG), The University of Glasgow is one of the top 20 research led universities in the UK from the Russell Group and one of the top 100 universities worldwide. It was established in 1451 and has 1500 undergraduate and 4900 postgraduate students. The Device Modeling Group from the Department of Electronics and Electrical Engineering led by Professor Asen Asenov represents the University in the TRAMS consortium.

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About Intel
Intel is the world's largest chip maker, and a leading manufacturer of computer, networking and communications products. Intel Barcelona Research Centre (IBRC) is one of the Intel Labs. Its activities focus on research in the areas of microarchitecture and compilers for future microprocessors with the objective of increasing their performance and reducing their energy consumption and cost, while delivering highly reliable systems. IBRC has a long experience in the area of resilient microarchitectures, and has published many papers in this area.

The IMEC is a world-leading independent research center in nanoelectronics and nanotechnology. Imec is headquartered in Leuven, Belgium, has staff of more than 1,650 people and revenue of 270 million euro. Imec's More than Moore research targets semiconductor scaling for the 22nm technology node and beyond. With its More than Moore research, imec invents technology for nomadic embedded systems, wireless autonomous transducer solutions, biomedical electronics, photovoltaics, organic electronics and GaN power electronics. Imec's research bridges the gap between the fundamental research at universities and RΆin the industry. It has unique processing and system know-how, intellectual property portfolio, state-of-the-art infrastructure, and a strong and worldwide network position.

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