Nanotechnology Now

Our NanoNews Digest Sponsors



Heifer International

Wikipedia Affiliate Button


android tablet pc

Home > Press > SEMATECH Engineers Achieve Breakthroughs

Abstract:
High-k technology for CMOS within reach at the 45 nm technology node

SEMATECH Engineers Achieve Breakthroughs Enabling Implementation of High-k Dielectrics at 45 nm Technology Node

Austin, TX | April 25, 2005

Using a selected set of tools and processes, SEMATECH engineers have achieved twin breakthroughs in channel mobility and reliability of high-k/metal gate transistors, putting high-k technology for CMOS within reach at the 45 nm technology node.

The SEMATECH advance involves a titanium nitride (TiN) metal gate on a hafnium silicate (HfSiO) dielectric with an equivalent oxide thickness (EOT) of roughly 10 angstroms (Å), with mobility at 90 percent of the universal mobility curve for silicon dioxide (SiO2), the historic gate dielectric material. These EOT and mobility metrics meet the 45 nm technology node specifications listed by the International Technology Roadmap for Semiconductors (ITRS).

The achievement caps a lengthy effort within SEMATECH's Front End Processes Division, and is part of a program to fully enable the eventual introduction of high-k/metal gate technology in volume manufacturing. The process is not expected to add significant cost to current CMOS product flows.

"SEMATECH's high-k process represents a significant step in the search for a complete solution to planar CMOS at the 45 nm node and beyond," said Byoung Hun Lee, manager of the Advanced Gate Stack Program. "We are also working to produce a dual metal gate that can work with this process. Plus, these breakthroughs have applications for specialty architectures, such as FinFETs or fully depleted SOI devices."

Tests of SEMATECH wafers at Yale University confirmed the quality of the high-k dielectrics, according to T.P. Ma, chairman of Yale's Department of Electrical Engineering. "The mobility results that we recently obtained on SEMATECH's test wafers were truly outstanding, which are consistent with the low densities of interface traps in these wafers. Having seen these results first-hand, I am a lot more optimistic than ever before about the practical implementation of high-k gate dielectrics in the foreseeable future."

In explaining the significance of the SEMATECH process, Lee said that new materials and techniques must be found for transistors as their size decrease into the deep sub-100 nm regime. One of the serious challenges the industry faces is developing new gate dielectric materials. For decades, silicon dioxide (SiO2) was a reliable dielectric, but as transistors have continued to shrink, the reliability of the SiO2-based gate dielectric is reaching its physical limits, while the technical challenges of using that dielectric are increasing rapidly.

One solution is to use other materials, such as hafnium-based metal oxides, for gate dielectrics. These high-k materials, so-called because of their high dielectric constant (k), can be made much thicker than SiO2 while achieving the same gate capacitance - the ability to turn a gate on and off, allowing it to process data. SEMATECH has aggressively pursued the high-k option for the past eight years, in broad collaboration with several universities and equipment suppliers to identify materials and processes in time to meet member company and industry manufacturing needs.

Lee noted that in order to implement metal/high-k technology at the 45 nm node, slated by the ITRS for initial volume production in 2010, metal/high-k devices must perform well in three areas: mobility, reliability, and threshold voltage (Vth) controllability.

Mobility is the speed at which an electron can travel through a material, such as silicon channel region. Critical to electron mobility in a silicon-based transistor is the interface between silicon and the gate dielectric, with the SiO2 gate dielectric setting the standard. While high-k dielectrics historically have tended to show low electron mobility, SEMATECH's Hf-silicate performed at 90 percent of universal mobility, which is very close to a SiO2-based gate dielectric at similar EOT.

Also, Lee said SEMATECH's Hf-silicate process demonstrated exceptional results not only for mobility, but also for reliability, as measured by Vth instability. For an optimized process, the SEMATECH material reached one of the project's goals by showing a Vth instability of less than 10 millivolts (mV) after 1,000 seconds of constant voltage stress at 22 megavolts per centimeter (MV/cm). This result is about 10 times better than the comparable reliability of high-k materials typically shown in industry reports.

"What this means is that we have a high-k process with mobility similar to the heavily nitrided silicon oxynitride [SiON] dielectric which is currently in manufacturing, but with reduced gate leakage current," said Paul Kirsch, manager of SEMATECH's Advanced Gate Dielectric Project. "We have established a tool set and have identified several process parameters to reach this point." Kirsch added SEMATECH is making rapid progress in solving the challenge of Vth controllability and plans a subsequent announcement on that issue.

"This is a significant enabler for SEMATECH member companies to continue traditional planar CMOS transistor scaling," Lee said. "As manufacturers make their decisions on how to approach the 45 nm node, they will find that SEMATECH's work enhances the availability of high-k for that node. Our expectation is that within a year, we will resolve the key issues in the implementation of metal/high-k gates stack into conventional CMOS flow."

Lee credited Kirsch and SEMATECH engineers Naim Moumen, Prashant Majhi, Seungchul Song, Rino Choi and Gennadi Bersuker with developing these breakthroughs in the consortium's high-k dielectric process.

####

About SEMATECH
SEMATECH is a global semiconductor technology development consortium that has effectively represented the semiconductor manufacturing industry on innovation issues since 1988. SEMATECH conducts state-of-the-art research, and is a highly-regarded technology partner whose goal is to promote the interests common to all chipmakers. It has extensive experience collaborating with equipment and materials suppliers, as well as government and academic research centers, to refine the tools and technology necessary to produce future generations of chips.

Additional information may be found at www.sematech.org.

SEMATECH, the SEMATECH logo, AMRC, Advanced Materials Research Center, ATDF, the ATDF logo, Advanced Technology Development Facility, ISMI and International SEMATECH Manufacturing Initiative are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.


Contacts:
Dan McGowan
512-356-3440
dan.mcgowan@sematech.org

Copyright © SEMATECH

If you have a comment, please Contact us.

Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

Possible Futures

Air Force’s 30-year plan seeks 'strategic agility' August 1st, 2014

IBM Announces $3 Billion Research Initiative to Tackle Chip Grand Challenges for Cloud and Big Data Systems: Scientists and engineers to push limits of silicon technology to 7 nanometers and below and create post-silicon future July 10th, 2014

Virus structure inspires novel understanding of onion-like carbon nanoparticles April 10th, 2014

Local girl does good March 22nd, 2014

Chip Technology

Twisted graphene chills out: When two sheets of graphene are stacked in a special way, it is possible to cool down the graphene with a laser instead of heating it up, University of Manchester researchers have shown September 22nd, 2014

SouthWest NanoTechnologies (SWeNT) Receives NIST Small Business Innovation Research (SBIR) Phase 1 Award to Produce Greater than 99% Semiconducting Single-Wall Carbon Nanotubes September 19th, 2014

Toward optical chips: A promising light source for optoelectronic chips can be tuned to different frequencies September 19th, 2014

IEEE International Electron Devices Meeting To Celebrate 60th Anniversary as The Leading Technical Conference for Advanced Semiconductor Devices September 18th, 2014

Nanoelectronics

SouthWest NanoTechnologies (SWeNT) Receives NIST Small Business Innovation Research (SBIR) Phase 1 Award to Produce Greater than 99% Semiconducting Single-Wall Carbon Nanotubes September 19th, 2014

Rice rolls 'neat' nanotube fibers: Rice University researchers' acid-free approach leads to strong conductive carbon threads September 15th, 2014

Excitonic Dark States Shed Light on TMDC Atomic Layers: Berkeley Lab Discovery Holds Promise for Nanoelectronic and Photonic Applications September 11th, 2014

Researchers Create World’s Largest DNA Origami September 11th, 2014

Announcements

Immune system is key ally in cyberwar against cancer: Rice University study yields new two-step strategy for weakening cancer September 23rd, 2014

Los Alamos Researchers Uncover New Properties in Nanocomposite Oxide Ceramics for Reactor Fuel, Fast-Ion Conductors: Misfit dislocations are key to transport properties across material interfaces September 23rd, 2014

Production of Organometallic Frameworks in Least Possible Time September 23rd, 2014

New star-shaped molecule breakthrough: Scientists at The University of Manchester have generated a new star-shaped molecule made up of interlocking rings, which is the most complex of its kind ever created September 22nd, 2014

NanoNews-Digest
The latest news from around the world, FREE



  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More














ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project







© Copyright 1999-2014 7th Wave, Inc. All Rights Reserved PRIVACY POLICY :: CONTACT US :: STATS :: SITE MAP :: ADVERTISE