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The continuous downscaling of feature sizes in microelectronics according to Moore's law has already required the introduction of several "non-conventional" materials into the semiconductor manufacturing industry in recent years, such as Cu, high- and low- k dielectrics, etc.
For very advanced technology nodes (i.e.towards the 16nm node), bottom-up grown nanomaterials are also being considered for their potential as building blocks of devices and interconnections. Nanomaterials would not necessarily directly contribute to higher device densities, but their unique properties may solve specific issues linked to downscaling and would certainly enable a number of new device concepts and architectures.
Carbon Nanotubes (CNTs) and semiconductor Nanowires (NWs) are generally bottomup grown in a catalysed chemical vapour deposition (CCVD) fashion, i.e. with the mediation of metal nanoparticles. The formation of such nanoparticles by breaking up a thin catalyst film on the substrate, and the particle pre-growth treatment are key steps of the global growth process, which would literally only start when the precursor gases are brought into the chamber (Fig.1).
For microelectronics applications, it is essential that the growth process stays compatible with Si technology in terms of materials, tools and processes used, and also that it can be realised on wafer -scale. CNTs are mostly being considered as possible interconnects material, as replacement of Cu interconnects. The characteristic ballistic conduction of metallic CNTs, together with their high thermal conductivity (about 6000 W K m-1, compared to 400 W K m-1 for Cu), makes them particularly interesting for vertical interconnects in small vias (10 nm diameter and below) with high aspect ratios. The most favourable configuration would be the growth of high density single wall carbon nanotubes, although also multi-wall nanotubes would lead to an improvement as compared to Cu.
As shown in Fig.2, a high density (~1012 CNTs/cm2) carpet of aligned CNTs with a few nm diameter was grown at 650ºC in a PlasmalabSystem100, starting from a Fe/Ti bilayer catalyst. The plasma pre-treatment of the particles is key to such high density growth.
Semiconductor nanowires are ideal building blocks for both logics and memory devices. Their vertical wire geometry allows excellent control on the electrical field in the channel of a nanowire-based transistor thanks to the all-around gate. Also, the growth of segmented nanowires would enable the formation of high quality hetero-junctions of mismatched semiconductors, thanks to favourable elastic and plastic relaxation phenomena at the nanoscale. On the other hand, NWs are generally grown using Au catalyst particles. Au is a killer impurity in Si technology, and trials to use other metal catalysts have not been as successful. In Fig.3 we show the feasibility of Si NWs growth from indium nanoparticles, again in a PlasmalabSystem100. Indium is not an efficient chemical catalyst for the Si precursor dissociation, so the use of plasma-enhanced CVD growth, following a plasma-based particle pre-growth treatment of the In particles, is essential for a successful In -mediated nanowire growth.
Author: Francesca Iacopi, PhD, Senior Scientist, IMEC
(see full release for all three figures)
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