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Home > Press > Nanoscale Analog CMOS Design and Shortening Physical Design Time to Market

Abstract:
REMINDER: Lanny L. Lewyn, Tanner EDA Technical Advisor, Presents on Nanoscale Analog CMOS Design and Shortening Physical Design Time to Market at IEEE NORCHIP Event

November 15 & 16, 2009, Trondheim, Norway

Nanoscale Analog CMOS Design and Shortening Physical Design Time to Market

Trondheim, Norway | Posted on November 4th, 2009

Who:

Lanny L. Lewyn, Technical Advisor to Tanner EDA, the world leader in PC-based analog, mixed-signal (A/MS) and MEMS circuit design software, is giving a pre-conference tutorial and invited paper on Physical Design and Reliability Issues in Nanoscale Analog CMOS Technologies at the IEEE Nordic Microelectronics or NORCHIP event.

Dr. Lewyn is president of Lewyn Consulting Inc. (Laguna Beach, CA) and is a Life Senior Member of the IEEE. He holds 29 U.S. patents in CMOS and bipolar circuits, and B.S. Eng. and M.S.E.E. degrees from the California Institute of Technology, and a Ph.D. E.E. from Stanford University.


What:

Title

Physical Design and Reliability Issues in Nanoscale Analog CMOS Technologies

Abstract

Physical design deficiencies found after post-layout-extraction result in re-layout and a waste of the industry's most valuable commodity: time to market. This tutorial presents an overview of these effects on nanoscale analog circuit design and explores how to mitigate them.


When

Tutorial

13.00-17.00, Sunday, 15 November 2009

Invited Talk

09.15-10.00, Monday, 16 November 2009


Where


Rica Nidelven Hotel
Havnegata 1
NO-7400 Trondheim
Norway
More Information:

For more information about Tanner EDA, please visit www.tannereda.com

For more information about Norchip, please visit www.norchip.org.

####

About Tanner EDA
Tanner EDA is a leading provider of PC-based electronic design automation (EDA) software solutions for the design, layout and verification of analog and mixed-signal ICs and MEMS. Its solutions promote innovation by speeding designs from concept to silicon. Tanner EDA software is used by thousands of companies in markets ranging from consumer electronics, biomedical, wireless, imaging, power management, RF and photovoltaics. Founded in 1988, Tanner EDA has shipped over 25,000 licenses of its PC-based electronic design software to more than 4,000 customers in 67 countries. For more information on Tanner EDA products, visit www.tannereda.com.

HiPer Verify and HiPer Silicon are trademarks of Tanner Research, Inc.

All other trademarks and tradenames are the property of their respective owners.

About Tanner EDA Software

HiPer Siliconô is Tanner EDA's hallmark software suite for the design, layout and verification of A/MS, RF and MEMS ICs. It includes core functionality for schematic capture, analog circuit simulation and physical layout as well as advanced features that improve designer productivity; including the HiPer Verifyô foundry-compatible physical verification engine, Verilog-A simulation, an interactive autorouter and device layout automation. The entire Tanner EDA product line is available on Windows and Linux platforms.

Contacts:
Press Contact:
Georgia Marszalek
ValleyPR for Tanner EDA
+1 650 345 7477
Email Contact
Twitter: @ValleyPR

Copyright © Tanner EDA

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