Nanotechnology Now

Our NanoNews Digest Sponsors



Heifer International

Wikipedia Affiliate Button


android tablet pc

Home > Press > SEMATECH to Reveal Breakthroughs in Controlling Parasitic Contactt Resistance in Advanced CMOS Devices

Abstract:
Technical experts to showcase new research results in advanced gate stack, high mobility channels, and 3D interconnect TSVs at VLSI symposium.

SEMATECH to Reveal Breakthroughs in Controlling Parasitic Contactt Resistance in Advanced CMOS Devices

Kyoto, Japan | Posted on June 15th, 2009

SEMATECH's continued leadership in developing, screening, and characterizing new materials, tools, and processes that enable CMOS scaling and emerging technologies will be further demonstrated during the 2009 VLSI Technology Symposium on June 15-17, 2009, at the Rihga Royal Hotel in Kyoto, Japan.

In one area of investigation, technologists from SEMATECH's Materials and Emerging Technologies program have demonstrated significant reductions in Schottky barrier height and contact resistance that are critical for continued enhancement of device performance in future technology nodes.

As scaling continues, one of the most pressing concerns of CMOS technology beyond the 45 nm node is the contact resistance in source/drain regions, which comes from a relatively high Schottky barrier between n-type doped Si and nickel silicide. SEMATECH researchers will outline recent progress in exploring alternative interface structures, reducing the parasitic resistances of the source and drain regions and improving mobility.

"Through intense research and development efforts, SEMATECH has developed manufacturable solutions with new materials and interfaces that reduce source-drain parasitic resistance. These practical implementation approaches enable future advanced gate and high-mobility channels," said Raj Jammy, SEMATECH's vice president of emerging technologies. "We're continuing to push CMOS technology to the limits, while we test the feasibility of emerging next-generation technologies."

SEMATECH driven advancements in materials and device structure will be highlighted at the symposium, including the following:

∑ A newly offered focus session, "3D-System Integration," SEMATECH's director of 3D interconnect program, Sitaram Arkalgud, will deliver an invited talk highlighting the importance of 3D TSV integration for future technology generations.

∑ An expert panel discussion, "Key Technology Options for 16 nm CMOS and Beyond - Breaking the Barriers" will include SEMATECH's Raj Jammy.

∑ The panel "Is TSV 3D LSI's and Packaging Finally Ready or Is It Just Another Fantasy?," co-moderated by Sitaram Arkalgud, will address the question of which applications are driving the development of TSVs.

Additionally, experts from SEMATECH's Materials and Emerging Technologies program will present six technical papers:

* Gate First High-k/Metal Gate Stacks with Zero SiOx Interface Achieving EOT=0.59nm for 16nm Application* - Demonstrates for the first time a HfOx films with a zero low-k SiOx interface has better scalability than exotic higher-k materials, and is a practical, scalable option for today's industry-standard Hf-based high-k films.**

*V**th** Variation and Strain Control of High Ge% Thin SiGe Channels by Millisecond Anneal Realizing High Performance pMOSFET Beyond 16nm Node* - Explores key parameters for controlling threshold voltage variation and strain maintenance of gate first SiGe channel pMOSFETs.**

*Selective Phase Modulation of NiSi Using N-Ion Implantation for High Performance Dopant- Segregated Source/Drain n-Channel MOSFETs* - Investigates dual phase-modulated Ni silicide for reducing the Schottky barrier and series resistance in dopant-segregated source/drain nMOSFETs.

*CMOS Band-Edge Schottky Barrier Heights Using Dielectric-Dipole Mitigated (DDM) Metal/Si for Source/Drain Contact Resistance Reduction* -* *Demonstrates for the first time Schottky barrier height tuning using interfacial SiO2 and dual high-k dielectrics.

**A Scalable and Highly Manufacturable Single Metal Gate/High-k CMOS Integration for Sub-32nm Technology for LSTP Applications* - Outlines a simple, scalable gate-first integration option for manufacturing high-k metal gate CMOS transistors targeted for sub-32nm low standby power applications. **

*Mechanisms for Low On-State Current of Ge (SiGe) nMOSFETs: A Comparative Study on Gate Stack, Resistance, and Orientation-Dependent Effective Masses* - Reports the results of a systematic study to understand the low drive currents observed in Ge-based nMOSFETs.**

The International Symposium on VLSI Technology, Technology and Circuits is sponsored by the IEEE Electron Devices and Solid-State Circuits societies and the Japan Society of Applied Physics in cooperation with the Institute of Electronics, Information and Communication Engineers. VLSI Japan is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions, many of whom are research partners.

####

About SEMATECH
For over 20 years, SEMATECHģ (*www.sematech.org*), the global consortium of
leading semiconductor manufacturers, has set global direction, enabled
flexible collaboration, and bridged strategic R&D to manufacturing. Today,
we continue accelerating the next technology revolution with our
nanoelectronics and emerging technology partners.

For more information, please click here

Contacts:
Erica McGill
SEMATECH | Media Relations
257 Fuller Road | Suite 2200 | Albany, NY | 12203
o: 518-649-1041
m: 518-487-8256

Copyright © SEMATECH

If you have a comment, please Contact us.

Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

News and information

Stressed Out: Research Sheds New Light on Why Rechargeable Batteries Fail October 1st, 2014

New Absorber Will Lead to Better Biosensor: Biosensors are more sensitive and able to detect smaller changes in the environment October 1st, 2014

Graphene chips are close to significant commercialization October 1st, 2014

Production of Filters for Separation of Water from Petroleum Products in Iran October 1st, 2014

Chip Technology

Graphene chips are close to significant commercialization October 1st, 2014

Speed at its limits September 30th, 2014

Research mimics brain cells to boost memory power September 30th, 2014

'Pixel' engineered electronics have growth potential: Rice, Oak Ridge, Vanderbilt, Penn scientists lead creation of atom-scale semiconducting composites September 29th, 2014

Nanoelectronics

Grenoble Hosting SEMICON Europa Oct. 7-9, First Time Event Held in France: Letiís 90-square-meter Booth Will Feature Portable Showroom To Demonstrate New Technology Innovations September 24th, 2014

SouthWest NanoTechnologies (SWeNT) Receives NIST Small Business Innovation Research (SBIR) Phase 1 Award to Produce Greater than 99% Semiconducting Single-Wall Carbon Nanotubes September 19th, 2014

Rice rolls 'neat' nanotube fibers: Rice University researchers' acid-free approach leads to strong conductive carbon threads September 15th, 2014

Excitonic Dark States Shed Light on TMDC Atomic Layers: Berkeley Lab Discovery Holds Promise for Nanoelectronic and Photonic Applications September 11th, 2014

Announcements

Stressed Out: Research Sheds New Light on Why Rechargeable Batteries Fail October 1st, 2014

New Absorber Will Lead to Better Biosensor: Biosensors are more sensitive and able to detect smaller changes in the environment October 1st, 2014

Graphene chips are close to significant commercialization October 1st, 2014

Production of Filters for Separation of Water from Petroleum Products in Iran October 1st, 2014

Events/Classes

Yale University and Leica Microsystems Partner to Establish Microscopy Center of Excellence: Yale Welcomes Scientists to Participate in Core Facility Opening and Super- Resolution Workshops October 20 Through 31, 2014 September 30th, 2014

Oxford Instruments launches 3rd annual Indian nanotechnology seminars in Kolkata and Delhi - sharing expertise with Nanotechnology researchers in India September 25th, 2014

Grenoble Hosting SEMICON Europa Oct. 7-9, First Time Event Held in France: Letiís 90-square-meter Booth Will Feature Portable Showroom To Demonstrate New Technology Innovations September 24th, 2014

Contributing to the spirit of the IYCR 2014 September 24th, 2014

NanoNews-Digest
The latest news from around the world, FREE



  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More














ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project







© Copyright 1999-2014 7th Wave, Inc. All Rights Reserved PRIVACY POLICY :: CONTACT US :: STATS :: SITE MAP :: ADVERTISE