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Home > News > Finding Solutions to Continued Scaling Efforts

February 6th, 2007

Finding Solutions to Continued Scaling Efforts

Abstract:
Chen's discussion of variability was not about the chip-to-chip, wafer-to-wafer or lot-to-lot variability, which can be solved. Also, regional variability — both systematic and random — can be solved as well. "The most important problem that we can't solve is the local systematic and random variability," he said. "It's what's going to kill technology advancement in this industry."

With this in mind, Chen turned his attention toward plans for the future — with options being to extend silicon CMOS (plan A), subsystem integration (plan B) or investing in non-silicon FETs or beyond FETs (plan C). Plan B shows some promise, Chen noted, pointing to such schemes as board-level optical interconnects and, more importantly, 3-D integration. Although 3-D integration has been used at the packaging level for several years, considerable gains could be made at the chip stack level, and even more at the CMOS level, he said. Coupled with low-power design, 3-D integration could offer a potential solution for system performance.

Plan C — options beyond CMOS — include such things as photonics, spintronics, quantum computing, and atomic/molecular configurations. Where IBM is investing a lot of time and money, Chen said, is with carbon nanotubes. "We think this is the most realistic alternative to a charge-transport-based system," he said. "We don't want to totally disrupt the existing infrastructure, and we think the carbon nanotube is the closest in that respect." Although spintronics is very promising, he added, that infrastructure would require a considerable change from what the industry is doing today.

Source:
reed-electronics.com

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