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April 25th, 2005
A published road map for the semiconductor industry has the smallest distances between wires on a memory chip shrinking from 90 nanometers today to 65nm in 2007, to 45nm in 2010, to 32nm in 2013 and on down from there.
"What they are going to do 12 years from now is mapped out, but they don't have a clue how to do that," says (HP Labs' Duncan) Stewart. "In fact, they think they may not be able to do it."
The 32nm milestone is "a reasonable place for us to inject some of these ideas," he says. The idea isn't to replace silicon transistors but to build certain devices, such as ultradense memories, on top of CMOS chips. Stewart says HP hopes to eventually build crossbar devices smaller than 3nm.
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