- About Us
- Career Center
- Nano-Social Network
- Nano Consulting
- My Account
April 25th, 2005
A published road map for the semiconductor industry has the smallest distances between wires on a memory chip shrinking from 90 nanometers today to 65nm in 2007, to 45nm in 2010, to 32nm in 2013 and on down from there.
"What they are going to do 12 years from now is mapped out, but they don't have a clue how to do that," says (HP Labs' Duncan) Stewart. "In fact, they think they may not be able to do it."
The 32nm milestone is "a reasonable place for us to inject some of these ideas," he says. The idea isn't to replace silicon transistors but to build certain devices, such as ultradense memories, on top of CMOS chips. Stewart says HP hopes to eventually build crossbar devices smaller than 3nm.
|Related News Press|
Molecular trick alters rules of attraction for non-magnetic metals August 5th, 2015
Global Carbon Nanotubes Industry 2015: Acute Market Reports August 4th, 2015
Nanometrics to Participate in the Citi 2015 Global Technology Conference August 26th, 2015
A little light interaction leaves quantum physicists beaming August 25th, 2015
'Quantum dot' technology may help light the future August 19th, 2015
Better together: Graphene-nanotube hybrid switches August 3rd, 2015
Russia’s Nano-enabled Products Market to Witness Massive Growth February 8th, 2011
Adept Technology Announces Orders for Over $600K from Chinese Partner January 18th, 2011
Nanostart-held ItN Nanovation Receives Major Follow-on Order in Saudi Arabia November 29th, 2010
Homegrown Companies Developing Batteries for Clean Energy Storage November 2nd, 2010