Nanotechnology Now

Our NanoNews Digest Sponsors

Heifer International

Wikipedia Affiliate Button

Home > Press > SEMATECH Advances Device Processing Techniques to Enable III-V Manufacturing: Results show significant progress in developing a low-cost process technology to deposit III-Vs on top of silicon

Abstract:
SEMATECH announced today that researchers have made significant advances in post-epitaxial growth backside clean processing that will prepare III-V technology for high-volume manufacturing. The research leading to these accomplishments was conducted at SEMATECH's facilities at the College of Nanoscale Science and Engineering (CNSE) in Albany, NY.

SEMATECH Advances Device Processing Techniques to Enable III-V Manufacturing: Results show significant progress in developing a low-cost process technology to deposit III-Vs on top of silicon

Albany, NY | Posted on June 27th, 2013

Following a two-year effort to improve process parameters and validating III-V on 200 mm Si VLSI process flows, technologists have identified the key mechanisms to enable a robust backside cleaning process and made significant progress in reducing the likelihood of process cross-contamination that could impact a high-volume manufacturing line. This important milestone was presented during SEMATECH's Surface Preparation and Cleaning Conference held recently in Austin, Texas.

Furthermore, SEMATECH has developed systematic experiments to identify the key mechanisms of backside contamination, which were then used to engineer robust backside clean process using standard high-volume manufacturing toolsets. At the same time, researchers assessed the environmental, safety and health (ESH) risks of applying and processing compound semiconductor films on silicon dioxide wafers.

"In order to drive cost-effective compliance solutions, SEMATECH is developing new testing and analysis methodologies to evaluate ESH impacts of novel materials," said Hsi-An Kwong, SEMATECH's ESH Technology Center program manager. "After conducting a process analysis of III-V manufacturing line, we were able to identify potential ESH risks, including generation of arsine and arsenic compounds, and develop protocols to help mitigate the impact to environment and safety."

Supported by the conventional Si CMOS processing capabilities of CNSE, SEMATECH researchers are now working jointly with chipmakers, equipment and materials suppliers and universities on the ESH and contamination challenges of processing III-V materials in a 300 mm fab in order to enable safe implementation of III-V technology for high-volume manufacturing.

III-V compound semiconductors are considered valid candidates as building blocks for the implementation of high-performance, low-power logic devices beyond the 10 nm technology node. To be truly competitive, III-V based technology must be monolithically integrated with Si in order to benefit from the existing Si-based semiconductor processing. For successful introduction into a Si manufacturing line, hetero-integrated III-V on Si wafers must be processed with a backside clean and capping processes.

"Through the success of our research and development efforts, SEMATECH is developing manufacturable solutions and practical implementation approaches to enable the fabrication of logic devices and systems on chips with diverse and improved functionalities," said Paul Kirsch, director of Front End Processes (FEP) at SEMATECH.

For over half a century, silicon-based materials have been the basic layers used in the manufacturing of CMOS transistors; however, these staple materials, as well as materials derived from silicon such as insulators and contact metals, are reaching their limits as the industry looks to lower power dissipation in CMOS devices and as scaling approaches the physical limits of silicon transistors. SEMATECH's FEP program is exploring innovative materials, new transistor structures and alternative non-volatile memories to address key aspects of system-level performance, power, variability and cost to help accelerate innovation in the continued scaling of logic and memory applications.

"The backside clean step is a key component of successful introduction of III-V material to a 300 mm high-volume manufacturing line," said Chris Hobbs, SEMATECH's FEP program manager. "Success at this step is critical to ensure contamination control through subsequent toolsets."

####

About SEMATECH
For over 25 years, SEMATECH®, the international consortium of leading semiconductor device, equipment, and materials manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Through our unwavering commitment to foster collaboration across the nanoelectronics industry, we help our members and partners address critical industry transitions, drive technical consensus, pull research into the industry mainstream, improve manufacturing productivity, and reduce risk and time to market. Information about SEMATECH can be found at www.sematech.org. Twitter: www.twitter.com/sematech

For more information, please click here

Contacts:
Erica McGill
SEMATECH
Marketing Communications
O: 518-649-1041

Copyright © SEMATECH

If you have a comment, please Contact us.

Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

News and information

Ag/ZnO-Nanorods Schottky diodes based UV-PDs are fabricated and tested May 26th, 2017

New metamaterial-enhanced MRI technique tested on humans May 26th, 2017

Controlling 3-D behavior of biological cells using laser holographic techniques May 26th, 2017

Unveiling the quantum necklace: Researchers simulate quantum necklace-like structures in superfluids May 26th, 2017

Chip Technology

Researchers find new way to control light with electric fields May 25th, 2017

Nanometrics Announces Retirement Plans of CEO Timothy Stultz: Dr. Stultz to Continue as Director May 25th, 2017

GLOBALFOUNDRIES and Chengdu Partner to Expand FD-SOI Ecosystem in China: More than $100M investment to establish a center of excellence for FDXTM FD-SOI design May 23rd, 2017

Plasmon-powered upconversion nanocrystals for enhanced bioimaging and polarized emission: Plasmonic gold nanorods brighten lanthanide-doped upconversion superdots for improved multiphoton bioimaging contrast and enable polarization-selective nonlinear emissions for novel nanoscal May 19th, 2017

Announcements

Ag/ZnO-Nanorods Schottky diodes based UV-PDs are fabricated and tested May 26th, 2017

New metamaterial-enhanced MRI technique tested on humans May 26th, 2017

Controlling 3-D behavior of biological cells using laser holographic techniques May 26th, 2017

Unveiling the quantum necklace: Researchers simulate quantum necklace-like structures in superfluids May 26th, 2017

Events/Classes

Nanomechanics, Inc. to Exhibit at the SEM Conference: Nanoindentation experts will attend and exhibit their instruments at the Conference and Exposition on Experimental and Applied Mechanics in Indianapolis May 25th, 2017

Leti to Demo 1st Wireless UNB Transceiver for ‘Massive Internet of Things’ at RFIC 2017 and IMS 2017: Leti Will also Present Three Papers & Two Workshops on 5G Communications IC Design, from RF to mm-Wave, During IMS 2017 and RFIC 2017 in Hawaii May 24th, 2017

Leti Will Demo World’s-first WVGA 10-µm Pitch GaN Microdisplays for Augmented Reality Video at Display Week in Los Angles: Invited Paper also Will Present Leti’s Success with New Augmented Reality Technology That Reduces Pixel Pitch to Less than 5 Microns May 22nd, 2017

Oxford Instruments Asylum Research and Microscopy and Analysis Present the Webinar: “Video-Rate Atomic Force Microscopy Enables New Research Opportunities” May 9th, 2017

Alliances/Trade associations/Partnerships/Distributorships

California Research Alliance by BASF establishes more than 25 research projects in three years April 26th, 2017

BASF and Landa partner to create revolutionary pigments for automotive coatings: The alliance combines BASF innovations with Landa nano-pigment technology April 5th, 2017

Leti Announces EU/South Korean Project for World’s First 5G-system Prototype: Coinciding with the 2018 Winter Games in PyeongChang, Korea, Prototype Will Be First Time State-of-the-art Terrestrial Wireless Communication Is Seamlessly Combined with Disruptive Satellite Communicati April 4th, 2017

ATTOPSEMI Technology Joins FDXcelerator Program to Deliver Advanced Non-Volatile Memory IP to GLOBALFOUNDRIES 22 FDX® Technology Platform: Leading-edge I-fuse™ brings higher reliability, smaller cell size and ease of programmability for consumer, automotive, and IoT applications March 27th, 2017

Research partnerships

Ag/ZnO-Nanorods Schottky diodes based UV-PDs are fabricated and tested May 26th, 2017

Three-dimensional graphene: Experiment at BESSY II shows that optical properties are tuneable May 24th, 2017

Zap! Graphene is bad news for bacteria: Rice, Ben-Gurion universities show laser-induced graphene kills bacteria, resists biofouling May 22nd, 2017

Sensors detect disease markers in breath May 19th, 2017

NanoNews-Digest
The latest news from around the world, FREE



  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More











ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project