Nanotechnology Now

Our NanoNews Digest Sponsors

Heifer International

Wikipedia Affiliate Button

Home > News > R&D Profile: Silicon on Ceramics - A New Concept for Micro-Nano-Integration on Wafer Level

March 24th, 2009

R&D Profile: Silicon on Ceramics - A New Concept for Micro-Nano-Integration on Wafer Level

Abstract:
One of the challenges of using nano effects and patterns in semiconductor devices is the realization of an intelligent and robust connection to the macro world.

Story:
LTCC (low temperature cofired ceramics) are established materials for "System in Package" solutions due to the integration of passive elements, such as capacitors or resistors, associated with short development times as well as simple and cheap processing. The advantages of reliability, thermal stability and chemically inert packages offered by ceramic interconnect devices are combined with thin film precision by means of a smart wafer level packaging process. Tough mechanical, electrical or fluidic coupling of nano elements without affecting their functionality is guaranteed by a fully silicon-ceramic wafer compound material. The method is based on a bonding procedure between a nano patterned silicon surface (modified Black Silicon) and LTCC. A LTCC tape with adapted TCE to silicon is joined with a silicon wafer by lamination and pressure assisted firing. This manufactured "Silicon-On-Ceramic"-substrate enables a wide range of design solutions, in witch several, unfired ceramic layers are prepared with vias, wirings and fluidic channels using standard LTCC-technologies. After sintering, the ceramic acts as a carrier system with electrical and fluidic properties.

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

News and information

X-ray photoelectron spectroscopy under real ambient pressure conditions June 28th, 2017

Nanometrics to Participate in the 9th Annual CEO Investor Summit 2017: Accredited investor and publishing research analyst event held concurrently with SEMICON West and Intersolar 2017 in San Francisco June 27th, 2017

NMRC, University of Nottingham chooses the Quorum Q150 coater for its reliable and reproducible film thickness when coating samples with iridium June 27th, 2017

Picosunís ALD solutions enable novel high-speed memories June 27th, 2017

Chip Technology

Nanometrics to Participate in the 9th Annual CEO Investor Summit 2017: Accredited investor and publishing research analyst event held concurrently with SEMICON West and Intersolar 2017 in San Francisco June 27th, 2017

New TriboLab CMP Provides Cost-Effective Characterization of Chemical Mechanical Wafer Polishing Processes: Bruker Updates Industry-Standard CP-4 Platform for Most Flexible and Reliable Testing June 27th, 2017

Atomic imperfections move quantum communication network closer to reality June 25th, 2017

Research accelerates quest for quicker, longer-lasting electronics: UC Riverside-led research makes topological insulators magnetic well above room temperatures June 25th, 2017

Announcements

X-ray photoelectron spectroscopy under real ambient pressure conditions June 28th, 2017

Nanometrics to Participate in the 9th Annual CEO Investor Summit 2017: Accredited investor and publishing research analyst event held concurrently with SEMICON West and Intersolar 2017 in San Francisco June 27th, 2017

NMRC, University of Nottingham chooses the Quorum Q150 coater for its reliable and reproducible film thickness when coating samples with iridium June 27th, 2017

Picosunís ALD solutions enable novel high-speed memories June 27th, 2017

NanoNews-Digest
The latest news from around the world, FREE



  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More











ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project