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Home > News > R&D Profile: Silicon on Ceramics - A New Concept for Micro-Nano-Integration on Wafer Level

March 24th, 2009

R&D Profile: Silicon on Ceramics - A New Concept for Micro-Nano-Integration on Wafer Level

Abstract:
One of the challenges of using nano effects and patterns in semiconductor devices is the realization of an intelligent and robust connection to the macro world.

Story:
LTCC (low temperature cofired ceramics) are established materials for "System in Package" solutions due to the integration of passive elements, such as capacitors or resistors, associated with short development times as well as simple and cheap processing. The advantages of reliability, thermal stability and chemically inert packages offered by ceramic interconnect devices are combined with thin film precision by means of a smart wafer level packaging process. Tough mechanical, electrical or fluidic coupling of nano elements without affecting their functionality is guaranteed by a fully silicon-ceramic wafer compound material. The method is based on a bonding procedure between a nano patterned silicon surface (modified Black Silicon) and LTCC. A LTCC tape with adapted TCE to silicon is joined with a silicon wafer by lamination and pressure assisted firing. This manufactured "Silicon-On-Ceramic"-substrate enables a wide range of design solutions, in witch several, unfired ceramic layers are prepared with vias, wirings and fluidic channels using standard LTCC-technologies. After sintering, the ceramic acts as a carrier system with electrical and fluidic properties.

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