Nanotechnology Now





Heifer International

Wikipedia Affiliate Button


DHgate

Home > Press > UCLA scientists working to create smaller, faster integrated circuits

Abstract:
Major advances expected to lead to improved chips in cell phones, computers

UCLA scientists working to create smaller, faster integrated circuits

LOS ANGELES, CA | Posted on December 24th, 2007

Integrated circuits are the "brain" in computers, cell phones, DVD players, iPhones, personal digital assistants, automobiles' navigation systems and anti-lock brakes, and many other electronic devices.

A team of UCLA scientists has now demonstrated substantial improvements in integrated circuits, achieved not by costly improvements in manufacturing but by improved computer-aided design software based on better mathematical algorithms.

"We can get circuits designed with 30 percent less wire length using improved optimization than what we had demonstrated three years ago, based on circuits that were samples from industry," said Jason Cong, UCLA professor and chair of computer science. "We believe that when you apply these methods to current industry circuits, you will see similar gains. Industry says even 5 percent is very significant.

"We are showing there is another way to make major improvements, with better design and better architecture," added Cong, who has collaborated for nearly a decade with Tony Chan, UCLA professor of mathematics and the National Science Foundation's assistant director for mathematics and physical sciences.

The traditional way to achieve smaller, faster integrated circuits — also known as silicon chips — is by building smaller and smaller transistors and thinner wires. While the computer industry has made smaller, improved devices, Cong, Chan and their colleagues are improving the design of the chip itself.

A goal of the collaboration is the development of silicon chips that are faster and cheaper and consume less power than the current generation of chips, said Cong, who is also a member of the California NanoSystems Institute at UCLA.

"We think optimizing chip design is an exciting direction," he said.

Integrated circuits have a series of interconnected, nanosize nodes; the locations of the nodes on the chip's surface are very important because they can minimize the wire length on which the signal travels.

Nodes include tiny "logic gates," as well as much larger memory blocks and other functional blocks. There are tens of millions of nodes on a chip.

"We have found there is a huge amount of room for improvement in the physical design of the chip itself, including where nodes are placed," said UCLA mathematics graduate student Eric Radke, who works with Chan and Cong. "We want to minimize the wire length in each node."

A challenge, Cong said, is "how do you place the nodes on a two-dimensional surface with big pieces and small pieces that are all connected to one another? It's like a jigsaw puzzle with millions of pieces. How do you place them to minimize the total interconnections (wires) among them?"

"It's fairly easy to model this problem mathematically," Radke said. "You can think of the nodes as points on a giant graph, and you can think of the interconnects as hyper-edges that connect more than two nodes. We can use mathematics to determine how the placement problem should be solved. We use a mathematical technique called multiscale methods, in which we group nodes together until we get a mathematical problem that is small enough to solve."

Chan and Radke design algorithms for computer software to improve the placement of the nodes and are using differential equations that they build into the algorithms. The scientists expect that the research will lead to improved software for enhanced chip design. Cong's laboratory has found strong evidence that existing computer-aided programs for integrated circuit design are far from optimal.

Chan and Radke are now working to minimize the amount of time it takes a signal to get through a processor.

Research by Chan, Cong and their graduate students won the 2005 award for best paper at the International Symposium of Physical Design (ISPD). Their placement software, developed together with their former students Kenton Sze and Min Xie, also produced the best wire-length results in the 2006 Circuit Placement Contest organized by ISPD.

Chan and Cong are also working with Lieven Vandenberghe, UCLA professor and vice chair of electrical engineering, as well as computer science graduate student Guojie Luo and electrical engineering graduate student John Lee.

"It's great to come to the meetings and hear everybody's ideas because everybody comes from a different background," Radke said.

The research is funded by the National Science Foundation and the Semiconductor Research Corp., the world's leading university research consortium for semiconductors and related technology.

####

About UCLA
UCLA is California's largest university, with an enrollment of nearly 37,000 undergraduate and graduate students. The UCLA College of Letters and Science and the university's 11 professional schools feature renowned faculty and offer more than 300 degree programs and majors. UCLA is a national and international leader in the breadth and quality of its academic, research, health care, cultural, continuing education and athletic programs. Four alumni and five faculty have been awarded the Nobel Prize.

For more information, please click here

Contacts:
Stuart Wolpert,
(310) 206-0511

Copyright © UCLA

If you have a comment, please Contact us.

Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

Govt.-Legislation/Regulation/Funding/Policy

Could black phosphorus be the next silicon? New material could make it possible to pack more transistors on a chip, research suggests July 7th, 2015

A cool way to form 2-D conducting polymers using ice: POSTECH scientists develop breakthrough technique to easily optimize electrical properties of Polyaniline nanosheets to an unprecedented level in an environmental-friendly and inexpensive way July 7th, 2015

New technique enables magnetic patterns to be mapped in 3-D July 7th, 2015

Surfing a wake of light: Researchers observe and control light wakes for the first time July 6th, 2015

Chip Technology

Could black phosphorus be the next silicon? New material could make it possible to pack more transistors on a chip, research suggests July 7th, 2015

A cool way to form 2-D conducting polymers using ice: POSTECH scientists develop breakthrough technique to easily optimize electrical properties of Polyaniline nanosheets to an unprecedented level in an environmental-friendly and inexpensive way July 7th, 2015

Fundamental observation of spin-controlled electrical conduction in metals: Ultrafast terahertz spectroscopy yields direct insight into the building block of modern magnetic memories July 6th, 2015

Transition from 3 to 2 dimensions increases conduction, MIPT scientists discover July 6th, 2015

Announcements

Superconductor could be realized in a broken Lorenz invariant theory July 7th, 2015

New technique enables magnetic patterns to be mapped in 3-D July 7th, 2015

Crystal structure and magnetism -- new insight into the fundamentals of solid state physics: HZB team decodes relationship between magnetic interactions and the distortions in crystal structure within a geometrically 'frustrated' spinel system July 7th, 2015

Down to the quantum dot: Jülich researchers develop ultrahigh-resolution 3-D microscopy technique for electric fields July 7th, 2015

NanoNews-Digest
The latest news from around the world, FREE




  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More










ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project