- About Us
- Nano-Social Network
- Nano Consulting
- My Account
December 13th, 2007
The university-research consortium Semiconductor Research Corp (SRC) of Research Triangle Park, NC, USA is funding Scotland's University of Glasgow in a $2.5m, three-year project ( from 1 January) to identify the best p-channel material to scale minimum MOSFET feature sizes in CMOS devices (including gate length) down to the 8nm technology generation.
By exploiting compound semiconductor materials for the p-type channel, the Glasgow research is expected to enable the shrinking of silicon chips for a further 4-6 years beyond previous projections for the miniaturization roadmap .
|Related News Press|
Electro-optical switch transmits data at record-low temperatures: Operating at temperatures near absolute zero, switch could enable significantly faster data processing with lower power consumption March 20th, 2017
UC researchers use gold coating to control luminescence of nanowires: University of Cincinnati physicists manipulate nanowire semiconductors in pursuit of making electronics smaller, faster and cheaper March 17th, 2017
Rare-earths become water-repellent only as they age March 22nd, 2017
AIM Photonics Welcomes Coventor as Newest Member: US-Backed Initiative Taps Process Modeling Specialist to Enable Manufacturing of High-Yield, High-Performance Integrated Photonic Designs March 16th, 2017
Leti Coordinating Project to Adapt Obstacle-Detection Technology Used in Autonomous Cars for Portable and Wearable Systems: INSPEX to Combine Knowhow of Nine European Organizations to Create Portable and Wearable Spatial-Exploration Systems February 2nd, 2017
Next-gen steel under the microscope March 18th, 2017