Nanotechnology Now

Our NanoNews Digest Sponsors

Heifer International

Wikipedia Affiliate Button

Home > News > Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

May 26th, 2004

Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

Abstract:
STMicroelectronics today announced that ST, CEA-Leti and AIXTRON have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes. The new process significantly reduces transistor leakage current by the deposition of 'high-k' gate-insulation material.

Source:
Businesswire

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

Chip Technology

Nanometrics to Participate in the 9th Annual CEO Investor Summit 2017: Accredited investor and publishing research analyst event held concurrently with SEMICON West and Intersolar 2017 in San Francisco June 27th, 2017

New TriboLab CMP Provides Cost-Effective Characterization of Chemical Mechanical Wafer Polishing Processes: Bruker Updates Industry-Standard CP-4 Platform for Most Flexible and Reliable Testing June 27th, 2017

Atomic imperfections move quantum communication network closer to reality June 25th, 2017

Research accelerates quest for quicker, longer-lasting electronics: UC Riverside-led research makes topological insulators magnetic well above room temperatures June 25th, 2017

NanoNews-Digest
The latest news from around the world, FREE



  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More











ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project