Nanotechnology Now

Our NanoNews Digest Sponsors


Heifer International

Wikipedia Affiliate Button

Home > News > Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

May 26th, 2004

Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

Abstract:
STMicroelectronics today announced that ST, CEA-Leti and AIXTRON have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes. The new process significantly reduces transistor leakage current by the deposition of 'high-k' gate-insulation material.

Source:
Businesswire

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

Chip Technology

Quantum drag:University of Iowa physicist says current in one iron magnetic sheet can create quantized spin waves in another, separate sheet July 22nd, 2016

New Yale-developed device lengthens the life of quantum information July 22nd, 2016

New reaction for the synthesis of nanostructures July 21st, 2016

Research team led by NUS scientists develop plastic flexible magnetic memory device: Novel technique to implant high-performance magnetic memory chip on a flexible plastic surface without compromising performance July 21st, 2016

NanoNews-Digest
The latest news from around the world, FREE




  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More











ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project







Car Brands
Buy website traffic