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Home > News > Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

May 26th, 2004

Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

Abstract:
STMicroelectronics today announced that ST, CEA-Leti and AIXTRON have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes. The new process significantly reduces transistor leakage current by the deposition of 'high-k' gate-insulation material.

Source:
Businesswire

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