Nanotechnology Now

Our NanoNews Digest Sponsors

Heifer International

Wikipedia Affiliate Button

Home > News > Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

May 26th, 2004

Ultra-Thin Gate-Insulation Process for Advanced CMOS Transistors

Abstract:
STMicroelectronics today announced that ST, CEA-Leti and AIXTRON have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes. The new process significantly reduces transistor leakage current by the deposition of 'high-k' gate-insulation material.

Source:
Businesswire

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

Chip Technology

Geoffrey Beach: Drawn to explore magnetism: Materials researcher is working on the magnetic memory of the future April 25th, 2017

'Neuron-reading' nanowires could accelerate development of drugs for neurological diseases April 12th, 2017

Nanometrics to Announce First Quarter Financial Results on May 2, 2017 April 11th, 2017

AIM Photonics Presents Cutting-Edge Integrated Photonics Technology Developments to Packed House at OFC 2017, the Optical Networking and Communication Conference & Exhibition April 11th, 2017

NanoNews-Digest
The latest news from around the world, FREE



  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More











ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project