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March 22nd, 2004
TI to sample 65-nanometer chips in early 2005
Texas Instruments plans to sample a wireless product built with its 65-nanometer semiconductor manufacturing process technology in the first quarter of next year, the Dallas-based company said Monday. Offering details of its 65-nanometer CMOS process, the company said that it expects the new technology will reduce leakage power from idle transistors, such as when a cell phone is in standby mode, by a factor of 1,000.
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