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What would happen about the semiconductor memory in 2020 and beyond? SRC/NSF/A*STAR Forum on 2020 Semiconductor Memory Strategies held on 20-21 October 2009 at Data Storage Institute (DSI), Singapore is a good platform for all the participating members to learn the latest R&D trend on memory. 37 leading experts in the semiconductor memory field from US, New Zealand, Japan, Taiwan, Korea and Singapore gave invited talks in this forum. Through the panel discussions during the forum, it is expected to find out the promising research directions for emerging research memory devices, processes, and architectures as well as the most effective model for international cooperation in pre-competitive memory research that would foster rapid advances in memory technologies.
December 14th, 2009
SRC/NSF/A*STAR Forum on 2020 Semiconductor Memory Strategies: Processes, Devices, and Architectures - Prospectus
SRC/NSF/A*STAR Forum on 2020 Semiconductor Memory Strategies held on 20-21 October 2009 at Data Storage Institute (DSI) Singapore was organized by Semiconductor Research Corporation (SRC) and supported by US National Science Foundation (NSF) and Singapore Agency for Science, Technology and Research (A*STAR). Asia is an active region for the semiconductor memory research and development and there are many semiconductor memory key players in Asia such as Samsung in Korea; Toshiba, NEC, Tokyo Institute of Technology and AIST in Japan; Macronix and Elite Semiconductor Memory Technology (ESMT) in Taiwan; Chartered Semiconductor, Institute of Microelectronics (IME), DSI and National University of Singapore (NUS) in Singapore as well as others. Invited by A*STAR, SRC chose Singapore to host their first semiconductor memory forum out of US.
37 leading experts in the semiconductor memory field from US, New Zealand, Japan, Taiwan, Korea and Singapore gave invited talks in this forum. In addition to the experts from SRC and NSF, many other US leaders in the semiconductor memory field from Intel, GLOBAL FOUNDRIES, IBM, Texas Instruments (TI), Micron, Unity Semiconductors, RPI, SUNY Albany, UC Berkeley, Stanford Univ., Carnegie Mellon Univ., Univ. of Wisconsin, and also came to join this form and presented their research achievements. This forum provides good opportunities for all the speakers to know and learn from each other and it is a platform for the participating members to learn the latest R&D trend on memory. The Forum consistsed of six panel discussion sessions: novel memory devices, prospective materials for memory applications, memory architectures, technological platforms for future memories, physical limits of memory elements as well as needs and models for collaborative research. It is expected to find out the promising research directions for emerging research memory devices, processes, and architectures through the panel discussions during the forum.
The limits of scaling and performance for emerging semiconductor memories with an emphasis on embedded applications are still the focus of discussion. In addition to traditional non-volatile memories such as magnetoresistive random access memory (MRAM) and flash memory as well as volatile memories such as transistor-based static random access memory (SRAM) and capacitor-based dynamic random access memory (DRAM), the latest R&D achievements on new types of memories discussed on this forum include phase-change RAM (PCRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), zero capacitor RAM (Z-RAM), Polymer memories, Nanocrystal Based Nanotube/Nanowire memories, CNT based NEMS memories, spin torque transfer MRAM (STT-MRAM) and Thermal Assisted Switching MRAM (TAS-MRAM). The barriers and potential for voltage (power) and density scaling of different memory devices beyond the 22 nm ITRS node is one of hot topics for current semiconductor memory R&D. Possible solutions suggested by speakers are centered around new materials such as Si nanowires / nanotubes, carbon nano tubes (CNT), graphene and polymers, new memory elements such as memristor, gate-all-around transistor, nanowire diode and nanoCMOS, and new architecture design including the cross-point memory array with selection cell/diode, crossbar MRAM design, 3-D integration architectures and others. The advantages that nanostructures such as nanowires, nanotubes and graphene offer over their Si-based predecessors include their tiny size, low power consumption, good retention time and high density.
The invention of nonvolatile embedded memory with high speed and high density would imply a revolution in chip architectures, create new global applications, markets etc. 3D structure with Through Silicon Vias (TSV) for embedded memories could lead to dramatically different ways to build memories, including the low-power provisioning of high bandwidth and low latency. As an example, 3D specific design in the 3D FFT for radar processors can achieve 65% power reduction and 800% increase in memory bandwidth at the cost of 22% increase in total Si area. The primary challenge for the applications of 3D integration circuts (3D IC) is to overcome the cost issue through unique product advantage and reduced Si Area. Hybrid Nano/CMOS 3D integration could be the future of 3D ICs.
DRAM and SRAM remains the main workhorse in embedded memory for logic applications. The selection of DRAM or SRAM depends on the situation. Simply to say, if you need more memory, you should choose DRAM, but if you need fast memory, SRAM could be your first choice. ReRAM is a non-volatile memory with low power consumption, which can be created with very small feature sizes, allowing the scalability for future process generations. ReRAM is a very popular topic on this forum and the first target for ReRAM is to replace the NOL flash in the future. Dr Yoo from Samsung, Korea gave four research suggestions on ReRAM: 1) business model and product for ReRAM can be created by evolution patterns; 2) chaos and complexity phenomena should be considered in ReRAM studies; 3) reconfigurable logic may be one of promising areas for ReRAM applications; 4) Application of oxide ReRAM materials can be expanded to transparent oxide electronics including transparent sensors. The advantage for application of MRAM in the embedded memory includes unification of RAM/ROM, low-voltage operation, zero stand-by current and reduction of process steps. Perpendicular STT-MRAM is presented for solving the scaling issues for MRAM such as high writing current, low density, large switching field distribution (sensitive to process) and half selection issues (retention). There is a "battle" in the memory field and the wise selection should depend on the balance between power, performance, cost and environmental requirements.
Before closing, Dr Hillenius from SRC (USA) presented the SRC model for industry collaboration in his keynote address, highlighting on collaboration among competitors to fund relevant research in universities. Dr Kwong from IME (Singapore) also briefly introduced the Government-University-Industry collaborative model in Singapore. What model would work best for the memory industry? In particular, are there models for international cooperation in pre-competitive memory research that would foster rapid advances in memory technologies? What's the role of memory in More-than-Moore? How much scaling can we continue and what would we do with true 3-D memory system? Many emerging memory technologies show promising and most of them are discussed on this forum. We look forward to the new International Technology Roadmap for Semiconductor (ITRS) and see what happens in memory in 2020 and beyond.
|Group picture at the site visit to Fusionopolis organized by A*STAR|