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Home > Nanotechnology Columns > FEI > New Challenges in Imaging and Analysis for Semiconductor Design and Manufacturing

Dan Fineberg
FEI Global Marketing Manager, NanoElectroincs
FEI Company

Abstract:
Volume economics drives the business models of leading semiconductor manufacturers. They invest many billions of dollars per year in capital to get new designs to market faster, to ramp to volume faster, and to improve yields on new process technologies.

June 8th, 2007

New Challenges in Imaging and Analysis for Semiconductor Design and Manufacturing

Implications of Smaller Semiconductor Geometries
Volume economics drives the business models of leading semiconductor manufacturers. They invest many billions of dollars per year in capital to get new designs to market faster, to ramp to volume faster, and to improve yields on new process technologies.

The capital investments enable the production of larger wafers (moving to 300mm) containing more die at smaller line widths (moving to 45nm and below). Among other things, the combination of larger wafers and smaller line widths means greater return on capital, and more gross profits for the manufacturers. It also means more value for consumers, businesses and governments who purchase electronics products.

But these new process technologies also introduce new challenges for validating new chip designs and for developing and controlling manufacturing processes. In both areas, more precise imaging and analysis is required to isolate faults, analyze failures, make critical measurements, and generate the data used to correct inevitable design and process flaws.



Semiconductor Design Validation

Validation of chip designs traditionally involved an iterative succession of changes to photo masks (which help translate the circuit layout into actual silicon devices). Prototype devices were tested, and masks were modified to try to fix whatever problems showed up in the tests. The mask changes led to new tests, leading to new mask modifications, and the cycle would repeat until the test results met the device's design specifications. Each cycle could take months and cost millions to produce new mask sets.

Today, leading chip companies employ focused ion beam (FIB) circuit editing to improve time-to-market. FIBs can image the circuits, but more importantly, can remove and deposit insulator and conductor materials to "re-wire" around flaws or to make circuit performance improvements. That material removal and deposition is done with the aid of chemical gases.

FIB circuit editing eliminates iterative cycles of prototype testing and mask modification. The FIB-edited device prototypes are used to guide modifications to masks one time - no more trial and error with successive versions of masks. But as geometries shrink, editing smaller circuits requires more precise FIB imaging and material removal and deposition. The risk of damaging surrounding circuitry also increases. In addition, new materials present new circuit edit challenges.

To meet all those challenges, a new generation of FIB tools is emerging that offers versatile gas delivery systems, enabling the FIB operator to apply variable pressures of a wide variety of gases for superior control and optimization. The ability to inject gases through dual, opposing nozzles provides the best quality dielectric deposition material for insulating critical regions of an edit. A dual nozzle based delivery is also invaluable for maintaining floor uniformity or planarity while accessing lower metal layers of a device. In addition, this new generation of FIB tools includes advanced software to improve editing precision and end-pointing control.



Semiconductor Manufacturing Process Development & Control

Process development and control for semiconductor manufacturing becomes more challenging as line widths shrink to less than 45nm. The "forensics" to find and fix process issues often requires imaging and measurement at magnifications and resolutions that exceed the capabilities of conventional scanning electron microscope (SEM) tools. Scanning transmission electron microscopes (STEMs) and transmission electron microscopes (TEMs) offer the required resolution and magnification, but they require preparation of thin sample lamellas. Until recently, that preparation was a slow, laborious process.

In addition, semiconductor manufacturers who produce high volumes of chips from a given design need to sample whole wafers from the line, inspecting many dies on each. Waiting for the wafers to be broken up before the samples are prepared causes unacceptable delays, especially when the manufacturing process is ramping to volume production. So semiconductor labs that support process development and control for volume manufacturing have been caught in a bind. Time-efficient SEM imaging may lack the necessary magnification and resolution, but higher-resolution/higher magnification STEMs and TEMs require time-consuming sample preparation -- and those delays are compounded by the lack of wafer-sized stages on those tools.

Many of those problems are addressed by a new generation of wafer DualBeam/STEM systems. The new tools integrate wafer DualBeam technology and a STEM detector for low-voltage STEM imaging, and they also include in-situ TEM sample lift-out and handling. Such innovations enable semiconductor labs to prepare, image and analyze wafer samples in one system, with far higher-throughput than previously possible.



Conclusion

Shrinking chip geometries and larger wafer sizes bring new opportunities and challenges to the semiconductor industry. They mean greater return on capital and greater customer value, but they also require new approaches for the "forensics" required to validate new designs and develop and control new manufacturing processes.
Circuit editing is a far better and faster approach to prototyping design fixes compared to repeated mask iterations. But as chip geometries move to less than 45nm, and new materials are used, FIB circuit edits must be more precise, and gas chemistries must be more flexible. Next-generation ion columns and advanced detector technology are critical to circuit edit success. Combined as an integrated solution with effective end-pointing and highly selective gas chemistries, FIB users will have the tools to perform highly successful device modifications on less than 45nm nodes.

For less than 45nm manufacturing process development and control, TEM and STEM imaging and analysis provide the necessary resolution and magnification. But sample preparation and handling cause frustrating delays. A new generation of wafer DualBeam/STEM systems delivers data much faster than had been possible before by working with whole wafers and by integrating sample preparation, imaging and analysis functions in one system. The result of that will be much higher throughput STEM sample preparation, imaging and analysis, and that means faster time to data, faster time to market, faster ramp to volume, and higher yields for semiconductor manufacturers.

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