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CEA-Leti, coordinator of a new European project targeting a breakthrough innovation in the field of fault-tolerant chip design, said today that the six members of the consortium will focus on developing innovative solutions allowing reliable circuits to be designed from low-power unreliable components.
One of the most critical challenges for next-generation electronic circuit design is the nanoscale integration of chips built of unreliable components. The inevitable integration- density increase and the requirements of low-energy consumption, for energy preservation, can only be sustained through inherently unreliable low-power components. The design of storage, interconnect, and processing elements will require completely new approaches involving powerful fault-tolerant techniques.
The i-RISC (Innovative Reliable Chip Designs from Unreliable Components) project, launched this year by the European Commission, builds on techniques from the sparse- graph codes theory, graph-based multi-objective optimization, and logic synthesis. It targets the design of effective error-correcting codes and encoder/decoder architectures able to provide reliable error protection even if they themselves operate on unreliable hardware. The envisaged fault-tolerant codec will contribute to the reliable storage and transfer of digital information throughout the chip. i-RISC will also develop a specific method to embed the codec into the structural description of the circuit logical functionality, to achieve reliable data processing. The proposed solution will be assessed and validated based on accurate error models and energy measurement tools developed within the project.
The i-RISC project will leverage the complementary and wide-ranging expertise of the six partners to cover all aspects of the research. In addition to CEA-Leti, the consortium includes University College Cork, (UCC, Ireland), Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA, France), Technische Universiteit Delft (TUD, The Netherlands), Universitatea Politehnica Timisoara (UPT, Romania), and University of Nis, Faculty of Electronic Engineering (ELFAK, Serbia).
"This project is seen by the consortium partners as a first step toward a new generation of fault-tolerant chips, which could greatly reduce their energy requirements, and therefore their impact on the environment," said Valentin Savin, researcher and project coordinator at CEA-Leti. "This is perfectly aligned with CEA-Leti's strategic objectives, namely the development of ‘green' ICT and computing systems. We expect the solutions developed in this project will enable a significant gain in chip robustness and a powerful reduction in energy-consumption."
Based on i-RISC's alignment with the target outcomes of the European Commission Work Programme, the project will provide strong and direct contributions to key areas that will improve the competitiveness of European academic research and industry in future ICT developments. In the forthcoming challenge of nanoscale technologies, the i-RISC project is an essential prerequisite for convincing European industry of the added value and feasibility of this new design approach.
Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defence and security. Leti is focused on creating value and innovation through technology transfer to its industrial partners. It specializes in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics. NEMS and MEMS are at the core of its activities. An anchor of the MINATEC campus, CEA-Leti operates 8,000-m2 of state-of-the-art clean room space on 200mm and 300mm wafer platforms. It employs 1,700 scientists and engineers including 240 Ph.D. students and 200 assignees from partner companies. CEA-Leti owns more than 1,880 patent families.
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