Nanotechnology Now

Our NanoNews Digest Sponsors

Heifer International

Wikipedia Affiliate Button

Home > Press > Novel 3D integration process flow: backside ‘soft’ via reveal

Figure 3D integration_1: Wafers are thinned down to 50µm thickness, with a total thickness variation of less than 2µm.
Figure 3D integration_1: Wafers are thinned down to 50µm thickness, with a total thickness variation of less than 2µm.

Abstract:
Imec presents a via-middle through-Si-via (TSV) approach to 3D stacking. This method is new to industry as it allows to ‘reveal' TSV contacts by using a Si-etch process. The process further allows thinning down the wafers to 50µm with a total thickness variation of less than 2µm.

Novel 3D integration process flow: backside ‘soft’ via reveal

Leuven, Belgium | Posted on March 15th, 2012

In the new 3D integration flow, a TSV contact is buried in the wafer during front-side processing. After completion of the wafer processing, the wafer is thinned and the bottom side of the TSV contacts are ‘revealed' in order to contact to a next layer of a 3D stack.

This process is novel to IC manufacturing and has to be performed with great care, in order not to damage the devices. In the past year, great progress has been made with respect to the wafer-support system for handling 300mm wafers, thinned down to 50µm thickness. A total thickness variation (TTV) of the thinned wafer of less than 2µm has been achieved. Key step in this process is the bonding of the device wafer to a carrier wafer, prior to wafer thinning, by using a temporary adhesive. This material is stable during the subsequent process steps, but still allows for room temperature debonding of the thinned wafer upon completion of backside processing.

After wafer thinning, the backsides of the TSVs are successfully ‘revealed' using a Si-etch process. Both wet and dry processes can be used. Chemical mechanical polishing (CMP) of the Cu/Si surface is not used as it results in a high risk of contamination and has a high cost-of-ownership. An effective via reveal process has been obtained using wet etching, exposing the TSVs uniformly on the wafer backside. In this stage, the TSV nails are still protected by their barrier and liner layers.

The next step in the backside process consists of applying a backside passivation layer (this avoids Cu diffusion in the thin Si wafer) and selective opening of the liner layers on the TSV. This is achieved using a maskless, self-aligned dry etch-process.

After this ‘soft' via reveal process, further interconnect layers and bump interconnects can be processed on the wafer backside. The process is then completed by debonding the thin wafer from the carrier wafer and transferring the thin wafer to a dicing tape. This step can now be performed at room temperature. This process flow was successfully applied to a 300mm diameter wafer with active high-k/metal gate CMOS circuits.

####

For more information, please click here

Contacts:
Barbara Kalkis
Maestro Marketing & PR

Copyright © IMEC

If you have a comment, please Contact us.

Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

News and information

NUS researchers invent new test kit for quick, accurate and low-cost screening of diseases: Test results are denoted by a color change and could be further analyzed by a smartphone app, making it attractive as a point-of-care diagnostic device September 19th, 2018

Silver nanoparticles are toxic for aquatic organisms: A research team at the UPV/EHU-University of the Basque Country has analysed how zebrafish are affected in the long term by exposure to silver particles September 19th, 2018

Leti Announces EU Project to Develop Powerful, Inexpensive Sensors with Photonic Integrated Circuits: REDFINCH Members Initially Targeting Applications for Gas Detection and Analysis For Refineries & Petrochemical Industry and Protein Analysis for Dairy Industry September 19th, 2018

Researchers develop microbubble scrubber to destroy dangerous biofilms September 19th, 2018

Chip Technology

Researchers managed to prevent the disappearing of quantum information September 14th, 2018

New devices based on rust could reduce excess heat in computers: Physicists explore long-distance information transmission in antiferromagnetic iron oxide September 14th, 2018

New photonic chip promises more robust quantum computers September 14th, 2018

How a tetrahedral substance can be more symmetrical than a spherical atom: A new type of symmetry September 14th, 2018

Announcements

NUS researchers invent new test kit for quick, accurate and low-cost screening of diseases: Test results are denoted by a color change and could be further analyzed by a smartphone app, making it attractive as a point-of-care diagnostic device September 19th, 2018

Silver nanoparticles are toxic for aquatic organisms: A research team at the UPV/EHU-University of the Basque Country has analysed how zebrafish are affected in the long term by exposure to silver particles September 19th, 2018

Leti Announces EU Project to Develop Powerful, Inexpensive Sensors with Photonic Integrated Circuits: REDFINCH Members Initially Targeting Applications for Gas Detection and Analysis For Refineries & Petrochemical Industry and Protein Analysis for Dairy Industry September 19th, 2018

Researchers develop microbubble scrubber to destroy dangerous biofilms September 19th, 2018

NanoNews-Digest
The latest news from around the world, FREE



  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More











ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project