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Home > Press > SEMATECH to showcase innovations in high-k metal gate reliability, non-planar devices and resistive rams at IEDM 2011: Technical papers demonstrate emerging solutions for critical material and device gaps in next generation device technologies
Engineers from SEMATECH are scheduled to present four technical papers and participate in a panel discussion at the 57th annual IEEE International Electron Devices Meeting (IEDM), December 5-7, 2011, at the Hilton in Washington, DC.
Highlighting significant breakthroughs that address the growing need for higher performance and low power devices, SEMATECH experts will report on high mobility channel materials, improved high-k metal gate reliability advancements, advanced non-planar device doping approaches, and resistive RAM (RRAM) memory technologies for scaled CMOS and memory beyond the 15nm node.
Title: Comprehensive Physical Modeling of Forming and Switching Operations in HfO2 RRAM Devices
When: Tuesday, December 6, 4 p.m.
Where: Jefferson Room
This paper will examine a novel physical model of RRAM devices that describes the creation of conductive filaments during forming and electrical transport in high and low resistance states.
Title: Improved High-k/Metal Gate Lifetime via Improved SILC Understanding and Mitigation
When: Tuesday, December 6, 3:10 p.m.
Where: Lincoln Room
This paper will identify, for the first time, key factors impacting stress-induced leakage current (SILC) through a comprehensive reliability study of high-k/ metal gate nMOSFETs, including several process changes that promise to mitigate SILC. An approach to reducing SILC, thereby improving device lifetime, will be proposed.
Title: ALD Beryllium Oxide: Novel Barrier Layer for High Performance Gate Stacks on Si and High Mobility Substrates
When: Wednesday, December 7, 9:30 a.m.
Where: Columbia 5 and 7
This paper will analyze BeO films epitaxially grown on Si and GaAs substrates using a conventional atomic layer deposition (ALD) technique. Their superior physical and electrical properties demonstrate the feasibility of employing this novel oxide as a gate dielectric and barrier layer in a manufacturing environment.
Title: 300mm FinFET Results Utilizing Conformal, Damage Free, Ultra Shallow Junction (Xj~5nm) Formed with Molecular Monolayer Doping Technique
When: Wednesday, December 7, 3:15 p.m.
Where: Columbia 5 and 7
This paper will demonstrate a new, conformal, damage-free doping technique (monolayer doping) for 20nm FinFETs. This technique is a promising candidate to address key FinFET scaling issues such as series resistance and short channel control for the 15nm node and beyond.
Title: Is 3 Dimensional Integration at Best a Niche Play?
When: Tuesday, December 6, 8:00 p.m.
Location: International Ballroom Center
Sitaram Arkalgud, director of SEMATECH's Interconnect division, will join other distinguished industry experts, including Shekhar Borkar of Intel, SiYoung Choi of Samsung, John Lau of ITRI, and Jan Vardaman of Techsearch, Inc. The panel, moderated by IBM Fellow Subramanian Iyer, will explore critical 3D interconnect issues from each panelist's perspective and open the discussion to audience participation.
The IEDM conference draws an international audience of industry professionals for an intensive exploration of design, manufacturing, physics, and modeling of semiconductors and other electronic devices. The conference spotlights leading work from the world's top electronics scientists and engineers; it is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions, many of whom are research partners.
For over 20 years, SEMATECH® (www.sematech.org), the international consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.
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