Nanotechnology Now

Our NanoNews Digest Sponsors

Heifer International

Wikipedia Affiliate Button

Home > Press > SOI Industry Consortium announces FD-SOI technology offers substantial power advantages for next-generation mobile and consumer applications

Abstract:
The SOI Industry Consortium today announced results of an assessment and characterization of Fully-Depleted Silicon-on-Insulator (FD-SOI) technology, demonstrating that this advanced CMOS silicon technology is well suited to address the increasing low-power, high-performance requirements for mobile and consumer applications.

SOI Industry Consortium announces FD-SOI technology offers substantial power advantages for next-generation mobile and consumer applications

Boston, MA | Posted on February 11th, 2011

A joint collaboration between Consortium members—ARM, GLOBALFOUNDRIES, IBM, STMicroelectronics, Soitec, and CEA-Leti—has demonstrated key benefits of planar FD-SOI technology for these applications based on an ARM processor. Planar FD-SOI technology enables substantial improvements in performance and power consumption for next-generation mobile devices, delivering high-performance applications with rich multimedia and communications functionality, reduced power consumption and improved battery life.

As SoC designs increase in complexity to deliver the enhanced features required by today's mobile consumer, designers face the challenge of continuing to reduce the voltage while maintaining the stability of the SRAM bit-cells. Early benchmarks on FD-SOI technology demonstrate the ability to reduce the SRAM operating voltage by 100-150mV, thereby reducing memory power consumption up to 40 percent while maintaining the stability of the SRAM.

Using an ARM Cortex™ processor as a prototyping vehicle, a team of SOI Industry Consortium members demonstrated that planar FD-SOI technology enables designers to continue to decrease the voltage to reduce the overall power, while maintaining system performance.

The inherent benefits of FD-SOI can also significantly improve system performance as you transition from generation to generation. Traditionally, low-power manufacturing technology processes from one generation node to another yield a performance gain ranging from 20 percent to 30 percent. This assessment indicates that when the same transition also includes FD-SOI technology an additional 80 percent gain can be achieved beyond the traditional increase. This level of improvement can enable higher-performance handheld products while significantly reducing the overall system power, which translates into a superior user experience.

FD-SOI also provides a compelling manufacturing advantage compared to other potential solutions. Due to its advanced starting substrate, FD-SOI wafer processing is simpler for the chip manufacturer. The elimination of a considerable number of mask layers during transistor-formation processing drives simpler manufacturing process flow, and thereby a cost-efficient approach to further shrinking CMOS transistors.

"Through our collaboration, Consortium members have demonstrated the advantages of FD-SOI for mobile and consumer applications," said Horacio Mendez, Executive Director of the SOI Industry Consortium. "FD-SOI is a great option to improve the key metrics for mobile markets: power, frequency, manufacturability and most importantly cost efficiency."

"This implementation indicates that FD-SOI technology is an attractive alternative for those designing SoCs for advanced mobile devices," said Simon Segars, Executive Vice President and General Manager, ARM, Physical IP Division. "It also demonstrates a significant opportunity for our customers to produce leading low-power, high-performance consumer devices, while potentially lowering their system cost."

"FD-SOI represents a tremendous technology opportunity for low-power mobile designs," said Dr. Suresh Venkatesan, Vice President, Technology Development, GLOBALFOUNDRIES. "FD-SOI offers a number of potential benefits through simplified manufacturing integration and a compelling power and frequency proposition."

SOI, recognized as a green semiconductor technology, has been in high-volume manufacturing for over a decade, enabling high-performance computing, gaming and communications products, with hundreds of millions of SOI chips shipped. FD-SOI also allows for full design re-usability: all established design tools and methodologies are fully implementable. SOI wafer manufacturers have affirmed that the ultra-thin SOI wafers needed for FD-SOI meet all specifications and are ready for high-volume manufacturing.

"As the Chairman of the SOI Consortium, I am extremely excited about the potential that the FD-SOI technology can bring to the industry. The testing and modeling to date would indicate that FD-SOI offers an ideal combination to achieve ultra-low-power, high-performance and cost-effective manufacturability attributes. The consortium members are all working together on the development and technology evaluations, with assistance from process R&D, IP design, manufacturing members and the substrate suppliers," said Michael Cadigan, Chairman of the SOI Industry Consortium and General Manager, IBM Microelectronics, Systems & Technology Group.

SOI Consortium Executives will be available to discuss the results at the Mobile World Congress in Barcelona, 14-17 February 2011. Please contact Camille Darnaud-Dufour, or Horacio Mendez, to arrange an appointment.

Legal Note

The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.

####

About SOI Industry Consortium
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing innovation leaders from the entire electronics industry infrastructure, current SOI Industry Consortium members include: AMD, Applied Materials, ARM, BroadPak, Cadence Design Systems, CEA-Leti, FEI, Freescale Semiconductor, GLOBALFOUNDRIES, IBM, IMEC, Infotech,, Kanazawa Institute of Technology , KLA-Tencor, MEMC, Mentor Graphics, MIT Lincoln Laboratories, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain, UMC and Varian. Membership is open to all companies and institutions throughout the electronics industry. For more information, please visit www.soiconsortium.org.

For more information, please click here

Contacts:
Press Contact (all time zones):

Camille Darnaud-Dufour
Mobile : +33 (0) 6 79 49 51 43

Copyright © SOI Industry Consortium

If you have a comment, please Contact us.

Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

News and information

Chemical trickery corrals 'hyperactive' metal-oxide cluster December 8th, 2016

Researchers peer into atom-sized tunnels in hunt for better battery: May improve lithium ion for larger devices, like cars December 8th, 2016

Scientists track chemical and structural evolution of catalytic nanoparticles in 3-D: Up-close, real-time, chemical-sensitive 3-D imaging offers clues for reducing cost/improving performance of catalysts for fuel-cell-powered vehicles and other applications December 8th, 2016

Exotic insulator may hold clue to key mystery of modern physics: Johns Hopkins-led research shows material living between classical and quantum worlds December 8th, 2016

Chip Technology

Chemical trickery corrals 'hyperactive' metal-oxide cluster December 8th, 2016

Leti IEDM 2016 Paper Clarifies Correlation between Endurance, Window Margin and Retention in RRAM for First Time: Paper Presented at IEDM 2016 Offers Ways to Reconcile High-cycling Requirements and Instability at High Temperatures in Resistive RAM December 6th, 2016

Tokyo Institute of Technology research: 3D solutions to energy savings in silicon power transistors December 6th, 2016

Physicists decipher electronic properties of materials in work that may change transistors December 6th, 2016

Nanoelectronics

Chemical trickery corrals 'hyperactive' metal-oxide cluster December 8th, 2016

Leti IEDM 2016 Paper Clarifies Correlation between Endurance, Window Margin and Retention in RRAM for First Time: Paper Presented at IEDM 2016 Offers Ways to Reconcile High-cycling Requirements and Instability at High Temperatures in Resistive RAM December 6th, 2016

Physicists decipher electronic properties of materials in work that may change transistors December 6th, 2016

Journal Nanotechnology Progress International (JONPI) Volume 6, issue 2 coming out soon! December 5th, 2016

Announcements

Chemical trickery corrals 'hyperactive' metal-oxide cluster December 8th, 2016

Researchers peer into atom-sized tunnels in hunt for better battery: May improve lithium ion for larger devices, like cars December 8th, 2016

Scientists track chemical and structural evolution of catalytic nanoparticles in 3-D: Up-close, real-time, chemical-sensitive 3-D imaging offers clues for reducing cost/improving performance of catalysts for fuel-cell-powered vehicles and other applications December 8th, 2016

Exotic insulator may hold clue to key mystery of modern physics: Johns Hopkins-led research shows material living between classical and quantum worlds December 8th, 2016

Alliances/Trade associations/Partnerships/Distributorships

Infrared instrumentation leader secures exclusive use of Vantablack coating December 5th, 2016

Leti and Grenoble Partners Demonstrate World’s 1st Qubit Device Fabricated in CMOS Process: Paper by Leti, Inac and University of Grenoble Alpes Published in Nature Communications November 28th, 2016

Mechanism for sodium storage in 2-D material: Tin selenide is an effective host for storing sodium ions, making it a promising material for sodium ion batteries October 27th, 2016

Enterprise In Space Partners with Sketchfab and 3D Hubs for NewSpace Education October 13th, 2016

Research partnerships

Researchers peer into atom-sized tunnels in hunt for better battery: May improve lithium ion for larger devices, like cars December 8th, 2016

Exotic insulator may hold clue to key mystery of modern physics: Johns Hopkins-led research shows material living between classical and quantum worlds December 8th, 2016

Deep insights from surface reactions: Researchers use Stampede supercomputer to study new chemical sensing methods, desalination and bacterial energy production December 2nd, 2016

Quantum obstacle course changes material from superconductor to insulator December 1st, 2016

NanoNews-Digest
The latest news from around the world, FREE




  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More











ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project