Nanotechnology Now

Our NanoNews Digest Sponsors



Heifer International

Wikipedia Affiliate Button


android tablet pc

Home > Press > SEMATECH Researchers to Present Breakthrough Innovations in III-V MOSFETs, FinFETs and Resistive RAMs at IEDM

Abstract:
Workshops and technical papers outline emerging solutions for critical dimension scaling and material technology

SEMATECH Researchers to Present Breakthrough Innovations in III-V MOSFETs, FinFETs and Resistive RAMs at IEDM

Austin, TX and Albany, NY | Posted on November 8th, 2010

Revealing research breakthroughs, engineers from SEMATECH's Front End Processes (FEP) program will present technical papers at the 56th annual IEEE International Electron Devices Meeting (IEDM) from December 6-8, 2010, at the Hilton in San Francisco, CA.

SEMATECH experts will report on resistive RAM (RRAM) memory technologies, advanced Fin and nanowire FETs for scaled CMOS devices, high mobility III-V channel materials on 200mm silicon wafers in an industry standard MOSFET flow, and future ultra-low power tunneling FET devices— highlighting significant breakthroughs that address the growing need for higher performance and low power devices.

Additionally, SEMATECH will host invitational pre‑conference workshops on December 5. The workshops will focus on technical and manufacturing gaps affecting promising emerging memory technologies and III-V channels on silicon. Co-sponsored by Tokyo Electron and Aixtron, these workshops will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.

During the IEDM conference, SEMATECH's FEP experts will present research results at the following sessions:

* Session 6, Monday, Dec. 6 at 2 p.m.: Self-aligned III-V MOSFETS Heterointegrated on a 200 mm Si Substrate Using an Industry Standard Process Flow - demonstrates, for the first time, that III-V devices on silicon can be processed in a silicon pilot line with controlled contamination, uniformity and yield while demonstrating good device performance.

* Session 16, Tuesday, Dec. 7 at 9:05 a.m.: Prospect of Tunneling Green Transistor for 0.1V CMOS - investigates tunneling green transistors for low-voltage CMOS VLSI devices and circuits. Statistical data will show that sub-60mV/decade characteristics have been clearly demonstrated on 8 inch wafers. This work is an ongoing collaboration with Prof. Chenming Hu and his co-workers at University of California Berkeley. The results of the collaborative work will be presented by Professor Hu.

* Session 19, Tuesday, Dec. 7 at 4:25 p.m.: Metal Oxide RRAM Switching Mechanism Based on Conductive Filament Microscopic Properties - reports on critical conductive filament features controlling RRAM operations. The forming process is found to define the filament shape, which determines the temperature profile and, consequently, switching characteristics.

* Session 26, Wednesday, Dec. 8 at 9:55 a.m.: Contact Resistance Reduction to FinFET Source/Drain Using Dielectric Dipole Mitigated Schottky Barrier Height Tuning - shows, for the first time, a contact resistance reduction using dielectric dipole mitigated Schottky barrier height tuning on a FinFET source. This technique is very promising for emerging devices, alternative channel materials, and sub-22nm CMOSFETs, where the Schottky barrier height and resulting higher parasitic contact resistance are significant barriers for scaling.

* Session 34, Wednesday, Dec. 8 at 2 p.m.: Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si Stack on SOI - reports on a dual channel scheme for high mobility CMOS FinFETs.
The IEDM conference draws an international audience of industry professionals for an intensive exploration of design, manufacturing, physics, and modeling of semiconductors and other electronic devices. The conference spotlights leading work from the world's top electronics scientists and engineers; it is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions, many of whom are research partners.

####

About SEMATECH
For over 20 years, SEMATECH®, the global consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.

For more information, please click here

Contacts:
Erica McGill
SEMATECH Media Relations
257 Fuller Roadm Suite 2200
Albany, NY 12203
o: 518-649-1041
m: 518-487-8256

Copyright © SEMATECH

If you have a comment, please Contact us.

Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.

Bookmark:
Delicious Digg Newsvine Google Yahoo Reddit Magnoliacom Furl Facebook

Related News Press

News and information

Aculon Hires New Business Development Director December 19th, 2014

How does enzymatic pretreatment affect the nanostructure and reaction space of lignocellulosic biomass? December 18th, 2014

Silicon Valley-Based Foresight Valuation Launches STR-IP™, a New Initiative for Startups to Discover the Value of Their Intellectual Property December 18th, 2014

Iranian Scientists Use Nanotechnology to Increase Power, Energy of Supercapacitors December 18th, 2014

Chip Technology

Switching to spintronics: Berkeley Lab reports on electric field switching of ferromagnetism at room temp December 17th, 2014

Pb islands in a sea of graphene magnetise the material of the future December 16th, 2014

Stanford team combines logic, memory to build a 'high-rise' chip: Today circuit cards are laid out like single-story towns; Futuristic architecture builds layers of logic and memory into skyscraper chips that would be smaller, faster, cheaper -- and taller December 15th, 2014

Stacking two-dimensional materials may lower cost of semiconductor devices December 11th, 2014

Memory Technology

Switching to spintronics: Berkeley Lab reports on electric field switching of ferromagnetism at room temp December 17th, 2014

Stanford team combines logic, memory to build a 'high-rise' chip: Today circuit cards are laid out like single-story towns; Futuristic architecture builds layers of logic and memory into skyscraper chips that would be smaller, faster, cheaper -- and taller December 15th, 2014

Graphene layer reads optical information from nanodiamonds electronically: Possible read head for quantum computers December 1st, 2014

'Giant' charge density disturbances discovered in nanomaterials: Juelich researchers amplify Friedel oscillations in thin metallic films November 26th, 2014

Nanoelectronics

Stacking two-dimensional materials may lower cost of semiconductor devices December 11th, 2014

Defects are perfect in laser-induced graphene: Rice University lab discovers simple way to make material for energy storage, electronics December 10th, 2014

Nanoscale resistors for quantum devices: The electrical characteristics of new thin-film chromium oxide resistors that can be tuned by controlling the oxygen content detailed in the 'Journal of Applied Physics' December 9th, 2014

'Giant' charge density disturbances discovered in nanomaterials: Juelich researchers amplify Friedel oscillations in thin metallic films November 26th, 2014

Announcements

Aculon Hires New Business Development Director December 19th, 2014

How does enzymatic pretreatment affect the nanostructure and reaction space of lignocellulosic biomass? December 18th, 2014

Silicon Valley-Based Foresight Valuation Launches STR-IP™, a New Initiative for Startups to Discover the Value of Their Intellectual Property December 18th, 2014

Iranian Scientists Use Nanotechnology to Increase Power, Energy of Supercapacitors December 18th, 2014

Events/Classes

Bruker Introduces BioScope Resolve High-Resolution BioAFM System: Featuring PeakForce Tapping for Quantitative Bio-Mechanical Property Mapping December 16th, 2014

TCL Launches World’s Most Advanced TV in the World’s Largest Market: New Quantum Dot TVs with Color IQ™ Optics Deliver OLED-Quality Color at a Fraction of the Price December 15th, 2014

Stanford team combines logic, memory to build a 'high-rise' chip: Today circuit cards are laid out like single-story towns; Futuristic architecture builds layers of logic and memory into skyscraper chips that would be smaller, faster, cheaper -- and taller December 15th, 2014

PETA science consortium to present at Society for Risk Analysis meeting December 10th, 2014

NanoNews-Digest
The latest news from around the world, FREE




  Premium Products
NanoNews-Custom
Only the news you want to read!
 Learn More
NanoTech-Transfer
University Technology Transfer & Patents
 Learn More
NanoStrategies
Full-service, expert consulting
 Learn More










ASP
Nanotechnology Now Featured Books




NNN

The Hunger Project







© Copyright 1999-2014 7th Wave, Inc. All Rights Reserved PRIVACY POLICY :: CONTACT US :: STATS :: SITE MAP :: ADVERTISE