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CEA-Leti will highlight its programs and recent developments in lithography, FDSOI and 3D design and integration at SEMICON Europa, Oct. 19-21 in Dresden, Germany.
Leti experts will be in Hall 4 - Booth 026.
Working with IBM, ST, Nikon, TSMC and other technology pioneers, CEA-Leti's Lithography Laboratory is developing production-oriented patterning for several generations of future semiconductor technology.
Lithography processes based on optical technology will likely not be effective beyond the 22nm node, and the most-discussed alternative, extreme ultraviolet, is still not ready for production after more than 15 years of development. Today, a cloud of uncertainty hangs over the semiconductor industry's ability to continue its historic progress to ever-smaller features.
Leti's Lithography Laboratory is addressing this challenge in several areas. The Imagine Program is cultivating maskless electron-beam lithographic approaches originally developed in Leti's ML2 maskless lithography program. Meanwhile, ongoing research into optical double-patterning techniques was applied to a spacer process for advanced logic chip production.
These efforts have placed Leti at the forefront of e-beam lithography, with one of the most advanced equipment sets in the world, including two shaped e-beam systems, two Gaussian-beam systems, and the alpha version of Mapper Lithography's multi-beam tool, which has the potential to bring huge boosts in productivity. The Lithography Laboratory also maintains a complete 193nm lithography capability, including data preparation and resist characterization.
Leti is focusing on the development of fully depleted silicon-on-insulator (FDSOI) technology, which potentially will enable fabrication of smaller, denser and faster integrated circuits.
FDSOI devices typically require a much thinner active silicon layer than standard complimentary metal-oxide semiconductor (CMOS) devices, while also enabling significantly reduced threshold voltage variability and enhanced speed/power tradeoff. These and other performance advantages suggest that FDSOI CMOS devices have the potential to be scaled down to the 10nm-technology node by tuning the buried-oxide and silicon-layer thicknesses.
Since pioneering SOI technology in the early 1990s, Leti has produced the most advanced research in FDSOI, assessing its key advantages for low-power, high-performance applications with several industrial partners.
Last year, Leti focused on developing 22nm FDSOI devices and models, while working locally with STMicroelectronics and the Soitec Group, as well as with IBM's semiconductor Joint Development Alliance in Albany, N.Y. In addition, Leti and CMP (Circuits Multi Projects®) launched an exploratory multi-project-wafer initiative based on FDSOI 20nm process, opening access to Leti's 300mm infrastructure to the design community.
Leti is offering wafer-to-wafer 3D integration support for customers' prototype development.
Leti researchers have been developing 3D design and integration technologies for more than two decades. Today, more than 60 researchers across several laboratories are working on various ways to make electrical connections between integrated circuit layers and between vertically stacked computer chips.
Potential uses for 3D integration span the electronics spectrum, from 3D networks-on-a-chip to memory-on-logic stacking to silicon-board technologies that could eventually replace printed-circuit-board packaging. 3D-IC technology plays a key role in enabling cost-effective performance for the entire microelectronics industry.
Leti is developing technologies that enable even higher-density vertical interconnects and recently integrated high-density, fine-pitch TSVs into a 65nm technology process, with very encouraging preliminary results.
Leti also started new 300mm TSV production processes in 300mm clean room facilities through a major partnership with SPP Process Technology Systems (SPTS). Leti will inaugurate its 3D integration 300mm on Jan. 18, 2011.
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