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Home > Press > Special feature: Un-masking a faster solution for chip-making

Abstract:
European researchers have developed a promising solution to mask-less' semiconductor lithography and generated intense interest among major industry players.

Mask-less lithography (ML2) promises to rapidly reduce the costs and production times associated with low-volume device manufacture and prototyping. A mask is a type of template that allows semiconductor manufacturers to print the circuit design onto a silicon wafer for microchip production.

Special feature: Un-masking a faster solution for chip-making

Europe | Posted on November 26th, 2008

But masks are very expensive and several are needed for one chip.

"The cost of masks is also rising as chip features become smaller and more sophisticated," explains Hans Loeschner, administrator of the RIMANA project.

The project was set up to demonstrate the feasibility of a new technique for mask-less lithography, called PML2, or Projection Mask-Less Lithography. It uses a variety of technologies in combination to burn a chip without a mask.

RIMANA's work has been wildly successful. The technology is now part of another EU-funded project, MAGIC, that will refine PML2 and examine alternatives, even though RIMANA will only finish its work in autumn 2008.

Better yet, the industry is already intensely interested in the work currently in completion. RIMANA's lead partner, IMS Nanofabrication, is in advanced talks with a leading industry player to develop the current prototype into a commercial model, possibly as early as 2011.
Further innovations

Leading industry figures like Dr Burn Lin, senior director of the lithography division of the Taiwan Semiconductor Manufacturing Company (TSMC), the leading semiconductor foundry in the world, believe that platforms like the RIMANA PML2 technology could have a very long life.

Further development on the RIMANA concept, Lin believes, could push the technology to respond to even greater challenges in the semiconductor lithography space.

Semiconductor lithography is essentially printing for microchips. The chips are printed with the tiny channels, gates and transistors that make up modern integrated circuits (ICs).

"Just like the printing industry, you have different printing machines for different purposes. A newspaper would have an enormous printer installation, that would be like Intel or AMD producing microprocessor chips or Micron and Samsung printing memory chips, but other solutions are needed for small print-runs and one-off projects," explains Dr Loeschner.

As semiconductors for all applications become more sophisticated, current solutions to the problem are no longer adequate to meet demand. "The industry needs a cost effective and fast system, and now. There is already demand for a system that can produce chips for low-volume applications, for device development and for rapid prototyping," Dr Loeschner reveals.
New twist on old idea

The EU-funded RIMANA project looked at a combination of established technologies for a radical potential solution. "The idea behind PML2 has been around for a long time, a similar system was proposed already in the 1980s, but there were problems that were impossible to solve at the time," Dr Loeschner states.

RIMANA's solution does not use a single Electron Beam Direct Write unit, which is normally used to make masks. Instead, the PML2 technology uses an electron beam that is directed to an aperture plate system that splits the beam into many thousands of smaller beams.

Next, a blanking plate may deflect individual beams. Only the un-deflected beams are projected to the silicon wafer surface to create a pattern, and that pattern is needed for the circuit fabrication.

But that simple explanation overlooks a large number of major innovations. For example, the company found a way to reduce by 200 the small beams produced by the aperture. "A 25mm diameter electron beam could be split into many hundred thousand micrometer- sized beams, and we then reduce those beams down to less than 20 nanometres," explains Dr Loeschner.
Testing technology

RIMANA tested its technology on 32nm and 22nm half-pitch (hp) circuit patterns. Half-pitch refers to a measure of lines and spaces to separate it from other elements within the circuit. A smallest resolution of just 16nm hp was achieved, surpassing the 22nm hp target of the RIMANA project.

Now, lead partner IMS Nanofabrication, together with the RIMANA partners, is putting the finishing touches to a programmable blanking plate. This uses an integrated CMOS (complementary metal oxide semiconductor) electronics to control beam deflection and is a major advance for the technology because it means that the patterns created by the PML2 system can be changed quickly.

All in all, it is a very complete, functioning proof-of-concept system. Within the MAGIC project, in 2008 a pre-commercialisation model is being realised followed, in 2009, by a PML2 Alpha Tool. Work remains to be done to make the system more robust, but it could be available commercially very soon.

The RIMANA project received funding from the ICT strand of the Sixth Framework Programme for research.

This is the first of a two-part special feature on RIMANA

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