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Home > Press > III-V Compounds Emerging as Prime Materials for Future NMOS Channels, Technologists Indicate at SEMATECH & AIXTRON Workshop during IEDM

Abstract:
The high electron mobilities of selected III-V compounds make them prime candidates for future NMOS channel materials, with an indium-based gallium-arsenide (InGaAs) likely to be the material of choice, industry experts agreed during a SEMATECH-led workshop at the IEEE International Electron Devices Meeting (IEDM).

III-V Compounds Emerging as Prime Materials for Future NMOS Channels, Technologists Indicate at SEMATECH & AIXTRON Workshop during IEDM

Washington, DC | Posted on December 18th, 2007

The invitational meeting, sponsored by AIXTRON AG and organized by SEMATECH, attracted more than 60 industry and university scientists to presentations from ranking technologists. The proponents of III-V expressed considerable excitement over the manufacturability of materials based on previously underused elements in columns III-V of the periodic table. InGaAs, with a mobility performance of 6-10 times that of silicon (Si), emerged as a leading channel material for dual channel devices that may consist of germanium-based PMOS and III-V-based NMOS field-effect transistors (FETs.)

At the same time, several industry experts expressed concern that these materials-based solutions for performance enhancement could not be brought to manufacturing in time, and that many issues that need to be addressed to realize performance improvement would not be resolved in time for devices at 22nm and beyond .

Technologists also agreed that inserting III-V materials on Si devices poses several challenges, including lattice mismatch, poor interface quality, high-k dielectric growth and off-state current leakage. However, the scalability of metal-organic chemical vapor deposition (MOCVD) attracted a consensus as the most promising manufacturing process, with clustered chambers for III-V and high-k suggested as an effective tool configuration for increased throughput. Opening speaker Robert Chau of Intel urged researchers to collaborate on resolving these and other issues, adding: "By 2012, we should have a real working solution for III-V."

The workshop, entitled "III-V CMOS on Si: Technical and Manufacturing Needs," also included a welcome speech by Raj Jammy, director of SEMATECH's Front End Processes Division. The speakers' panel consisted of Devendra Sadana of IBM, Max Fischetti of the University of Massachusetts, Suman Datta of Penn State University, Gene Fitzgerald of MIT, Matthias Passlack of Freescale Semiconductor, Peter Ye of Purdue University, and Rainer Beccard of AIXTRON. The workshop was moderated by Rusty Harris and Prashant Majhi of SEMATECH and by Zia Karim from AIXTRON.

At the IEDM technical sessions that followed, SEMATECH engineers revealed potentially breakthrough approaches for enabling high-k-metal gates and advanced channel engineering options by the 32-22nm technology generations.

Five papers presented by SEMATECH's Front End Processes (FEP) Division capped a year of solid progress by the consortium's technologists in developing a manufacturable high-k metal gate-stack solution for advanced device generations. The papers detailed a highly successful use of flash annealing, a new gate stack material for scaling EOT down to 0.85 nm, and new possibilities for performance improvement through use of alternate orientation Si surfaces and strained SiGe and Ge channels.

One paper, "Impact of Flash Annealing on Performance and Reliability of High-k/Metal-Gate MOSFETs for sub-45nm CMOS" whose lead author is FEP'S Pankaj Kalra, marked the successful use of millisecond annealing on scaled high-k metal gated devices to form ultra°©shallow junctions that meet requirements for sub-45nmn CMOS technology.

In this process, the wafers were ramped up to an intermediate temperature followed by using flash lamps to heat the device side of the wafer to the peak anneal temperature of 1300°C.

Subsequent testing revealed that flash annealing, unlike spike annealing, minimizes the dopant diffusion that causes excessive junction depths, and actually improves dopant activation. Also, the process does not significantly affect bulk charge trapping, one of the major performance/reliability issues in high-k dielectrics. The flash process can achieve junction depths around 12-15nm with low effective sheet resistance, a feat that meets 32nm technology targets.

A paper by lead author Rusty Harris explored the effectiveness of high-k metal gates built on the 110 silicon crystal plane. High-k/metal gates on NMOS Si(110) demonstrate respectable output performance due to velocity saturation of electrons, the authors found. "High-k seems to be an important element in making the 110 channel very realistic," Harris noted during his presentation.

Also, it appears that off-state current can be controlled in Si(110) in the same way as the more conventional Si(100) orientation, allowing Si(110) NMOS and PMOS structures to be used effectively in low standby power (LTSP) devices. As a result, Si(110) may provide significant performance improvement for high-performance (HP) and LTSP devices without the process complexity typical of mixed-orientation CMOS approaches.

Sagar Suthram served as lead author of a paper that discussed silicon-germanium with strained quantum wells (QWs) which could offer a replacement for silicon channels for 22nm and beyond, meeting future low-power and high-performance requirements that are probably too great for silicon-based materials. These QW devices - which utilize the quantum well effect of confining charge carriers to a two-dimensional plane, improving their transport characteristics - exhibit low band-to-band tunneling current and provide significant mobility enhancements. The QW devices display strain response similar to that of Si, indicating that scaling pathways with Ge-based devices exist.

SEMATECH engineers also released important new details on enabling approaches for dual metal gate technology:

Enriching high-k materials with oxygen in a low-temperature process is an effective way to diminish flat-band roll-off (Vfb), which is the main challenge to achieving low PMOS threshold voltage (Vt) and thin equivalent oxide thickness (EOT) at the same time. In developing this solution, FEP engineers discovered that progressive oxygen vacancy generation causes Vfb roll-off, shedding light on a little°©understood phenomenon. S.C. Song is lead author of this paper.

A second generation higher-k gate stack material, hafnium-titanium-silicon-oxynitride (HfTiSiON), has been demonstrated as an effective successor to first generation HfSiON gate dielectric materials. With an aggressively scaled dielectric constant (k) of around 40, and low leakage, HfTiSiON appears to answer gate stack manufacturability needs for the 32nm generation and beyond. "For the first time, we addressed the thermodynamic instability of TiO2°©containing dielectrics," said lead author Prasanna Sivasubramani. "This may enable gate stack scaling beyond HfO2."

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