Home > Press > IBM Alliances Deliver Easier Path to Next Generation Semiconductor Products
|32nm SRAM with High-K/Metal Gate - world's smallest SRAM cell using High-K/Metal Gate ( < 0.15um2)|
Smaller, Faster More Power-Efficient* 32 Nanometer Semiconductors Span Low-Power Consumer Devices, High-Performance Computing
IBM Alliances Deliver Easier Path to Next Generation Semiconductor Products
ARMONK, NY | Posted on December 10th, 2007
IBM (NYSE: IBM) and its joint development partners -- AMD, Chartered Semiconductor Manufacturing Ltd., Freescale, Infineon, and Samsung -- today announced an innovative approach to speed the implementation of a breakthrough material known as "high-k/metal gate" in next generation 32 nanometer (32nm) computer chips.
This new approach, an industry first based on what engineers call a "high-k gate-first" process, is designed to provide a simpler, less time consuming way for clients to migrate to high-k metal gate technology in order to secure benefits that include improved performance and reduced power consumption. Chips using the new technique will support a range of applications -- from low power computer microchips targeted at wireless and other consumer-oriented devices to high performance microprocessors for games and enterprise computing. This new approach to implementing high-k/metal gate will be available to IBM alliance members and their clients in the second half of 2009.**
On January 29, 2007, IBM and its research partners (including Sony and Toshiba) introduced the "high-k/metal gate" innovation as the basis for a long-sought improvement to the transistor -- the tiny on/off switch that serves as the basic building block of virtually all microchips made today. Using the high-k/metal gate material in a critical portion of the transistor that controls its primary on/off switching function enabled the development of 32nm chip circuitry that is designed to be smaller, faster, and more power-efficient than previously thought possible.
Using high-k/metal gate IBM and its Alliance Partners have been able to successfully shrink the size of a chip by up to 50 percent as compared to the previous technology generation while improving a number of other performance specifications. For example, high-k metal gate chips save about 45 percent total power, an increasingly critical metric in all electronics applications. Together these improvements will help to increase functionality and performance with lower power consumption and improved battery life in mobile devices. For microprocessor applications, this innovation also enables up to 30 percent higher performance as documented in measurements performed by IBM and its Alliance Partners at IBM's East Fishkill, NY semiconductor manufacturing facility.
"IBM's alliances have demonstrated the 'high-k gate-first' approach in a manufacturing environment, an achievement that provides clients with a simple, scalable pathway to incorporating the high k material innovation in semiconductor development without introducing additional design complexity," said Gary Patton, vice president, IBM's Semiconductor Research and Development Center on behalf of IBM's technology alliances. "This industry leading development comes from leveraging the collective engineering talent and breadth of market experience across the six Alliance Partner companies, as well as world-class R&D facilities such as UAlbany NanoCollege's Albany NanoTech complex, in order to maintain an aggressive road map."
IBM and its Alliance Partners have developed low-power foundry Complementary Metal Oxide Semiconductor (CMOS) technology using the 'high-k gate-first' approach and have demonstrated the first 32nm ultra dense static random access memory (SRAM) in this low power technology with cell sizes below 0.15um2. SRAMs are a key building block of computer chip designs and an excellent indicator of the readiness of a technology. The unique characteristics of the high-k material reduces total chip power consumption by as much as a 45 percent compared to the previous generation, a critical technology factor for achieving longer battery life in hand held devices such as cell phones, pagers, and PDAs.
In addition, IBM and its Alliance Partners have incorporated the high-k innovation into a new generation of high performance Silicon-On-Insulator (SOI) technology at 32nm. The unique high-k material properties enable a transistor speed improvement of greater than 30 percent over the previous generation of high performance Silicon-On-Insulator (SOI) technology. The SRAM demonstrated in this new generation of high performance technology functions at a lower voltage -- an improvement that reduces the energy consumption for microprocessor applications. The use of SOI provides a significant performance and power benefit, which, in combination with the high-k/metal gate advancement, will help the technology deliver energy efficient chips used in applications such as games, personal computers, and high end computing systems.
Today's announcement marks the latest development achievement from this alliance of semiconductor manufacturing, development and technology companies that collaborate to address the product design and advanced process development challenges central to producing a smaller, faster, more cost efficient generation of semiconductors.
* As documented in measurements performed by IBM and its Alliance Partners at IBM's East Fishkill, NY semiconductor manufacturing facility.
** All future dates and specifications are estimations only; subject to change without notice.
Note to Editors: A video is available in the IBM Press Room at http://www.ibm.com/press/us/en/pressrelease/22858.wss . A broadcast-quality version of the video can be downloaded by registered journalists at http://www.thenewsmarket.com/ibm .
For more information, please click here
AMD Public Relations
IBM Media Relations
Infineon Technologies AG
Phone +49 89 234 295 93
Fax +49 89 234 955 54 70
Mobile +49 160 530 4133
SSI Media Relations
Copyright © Marketwire
If you have a comment, please Contact
Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.
Bruker Launches ContourSP 3D Optical Microscope for PCB Industry: Large-Format Metrology System Debuts to Over $5 Million in Orders December 10th, 2013
Oregon scientists offer new insights on controlling nanoparticle stability: New findings could enhance stabilizing or destabilizing nanoparticles, depending on their uses December 9th, 2013
CWRU engineering researchers report nanoscale energy-efficient switching devices at IEDM 2013 December 9th, 2013
CEA-Leti Signs Agreement with Qualcomm To Assess Sequential 3D Technology December 9th, 2013
Synthesis of superconducting picene crystals December 12th, 2013
Iranian Scientists Discover New Electrical Device for Rapid Diagnosis of Cancer December 12th, 2013
3-D Analysis of Thermo-elastic Behavior of Composite Plate Graded with Carbon Nanotubes December 12th, 2013
Arrowhead to Report Fiscal 2013 Fourth Quarter and Year-End Financial Results - Conference Call Scheduled for Wednesday, December 18, 2013 December 12th, 2013
Secretary Vilsack Announces Partnership to Advance Commercial Potential of Cellulosic Nanomaterial from Wood December 11th, 2013
Cutting Away at the NRC's Research Capability December 6th, 2013
Dissolving electronics, energy: Kavli lectures at American Chemical Society meeting December 5th, 2013
Applied Nanotech Receives Contract From the Northeast Gas Association to Develop Methane Sensor December 4th, 2013