Home > Press > Cadence Announces New RF Technology to Ease Design of Nanometer Wireless Chips
Virtuoso Passive Component Designer Addresses Critical RF Challenges Through Proven Inductor Design, Analysis and Modeling
Cadence Announces New RF Technology to Ease Design of Nanometer Wireless Chips
SAN JOSE, CA | Posted on November 12th, 2007
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today introduced Cadence® Virtuoso® Passive Component Designer, a complete flow for the design, analysis and modeling of inductors, transformers and transmission lines. The new technology puts passive component design into the hands of analog and RF designers developing fast and complex wireless SoCs and RFICs. Starting from design specifications such as inductance, quality factor and frequency, the Virtuoso Passive Component Designer helps designers automatically generate the optimum inductive device for their specific application and process technology, resulting in higher performance and smaller area. A built-in accurate 3D full wave solver verifies the generated devices, eliminating the need for a dedicated inductor characterization run and reducing the design turnaround time.
Virtuoso Passive Component Designer is optimized for 90- and 65-nanometer process nodes, supporting advanced design rules and CMP constraints such as dummy metal fills and slotting. In addition to the wide variety of supported inductor and transformer geometries, it allows the design teams to define their own custom geometries graphically or manually using parameterized cells, or Pcells.
"Inductors and transformers are critical components in our high frequency integrated circuit. They have high impact on chip area and performance," said Hisaharu Miwa, general manager of the Design Technology Division, Renesas Technology Corp. "Our goal is to improve design productivity by considering the impact of inductors and transformers from the early design stages. We use Virtuoso Passive Component Designer because it addresses these challenges. Virtuoso Passive Component Designer provides an easy way to model and generate PDK components due to its integration in Virtuoso custom design platform and its accurate built-in electromagnetic solver."
Virtuoso Passive Component Designer is easy to use and does not require electromagnetic expertise. The output is a complete process design kit component with a symbol, schematic, layout and a simulation model. The built-in modeling capability converts S-parameter files into physical lumped element models, ready for RF analysis using Virtuoso Spectre® Circuit Simulator XL. The new Cadence technology also includes a fast and accurate coupling analysis capability enabling designers to optimize the placement of inductors and transformers on the layout resulting in smaller silicon area and higher yield.
"We immediately improved the frequency accuracy of our VCO designs to 0.9 to 1.9% once we adopted the Cadence RF Design Methodology Kit and began to use Virtuoso Passive Component Designer to accurately synthesize and model our inductors and transformers," said Dr. Aleksander Dec, vice president and co-founder, Epoch Microelectronics, Inc. "The combination of detailed inductor models from Virtuoso Passive Component Designer and accurate RLCK extracted views from QRC extraction enabled accurate full-chip sign-off. This represented a huge savings in both time and cost."
Virtuoso Passive Component Designer is tightly integrated into the Cadence Virtuoso custom design platform. The new technology is a component of Virtuoso Multi-Mode Simulation technology and follows the same flexible licensing scheme.
"The evolution of cellular phones and portable devices presents great challenges for analog and RF IC designers," said Srinivas Raman, corporate vice president, Virtuoso Custom IC R&D. "More and more complex analog and RF circuits need to fit in the same small lightweight handset, consume the same amount of battery power, and be produced with the same low cost of a single-band handset of the 1990s. Using the Virtuoso Passive Component Designer, analog and RF design teams can quickly create accurate passive components that meet design specifications, consume lower power and fit in smaller areas than pre-designed one-size-fits-all components."
About Cadence Design Systems, Inc.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, Virtuoso and Spectre are registered trademark, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please click here
Cadence Design Systems, Inc.
Copyright © Cadence Design Systems, Inc.
If you have a comment, please Contact
Issuers of news releases, not 7th Wave, Inc. or Nanotechnology Now, are solely responsible for the accuracy of the content.
Scientists open door to better solar cells, superconductors and hard-drives: Research enhances understanding of materials interfaces April 14th, 2014
Obducat has launched a new generation of SINDRE® Nano Imprint production system April 11th, 2014
Scientists in Singapore develop novel ultra-fast electrical circuits using light-generated tunneling currents April 10th, 2014
Clean Shot at Manufacturing Course…For Less April 9th, 2014
UT Arlington physicist creates new nanoparticle for cancer therapy April 16th, 2014
Relieving electric vehicle range anxiety with improved batteries: Lithium-sulfur batteries last longer with nanomaterial-packed cathode April 16th, 2014
Aerotech X-Y ball-screw stage for economical high performance Planar positioning April 16th, 2014
Energy Research Facility Construction Project at Brookhaven Lab Wins U.S. Energy Secretary's Achievement Award April 16th, 2014