Home > Press > This High Speed VLSI Interconnections 2nd Edition Focuses on Emerging Topics and Advances in This Field
Research and Markets ( http://www.researchandmarkets.com/reports/c73747 ) has announced the addition of "High-Speed VLSI Interconnections, 2nd Edition" to their offering.
This High Speed VLSI Interconnections 2nd Edition Focuses on Emerging Topics and Advances in This Field
DUBLIN, Ireland | Posted on November 6th, 2007
In the decade since High-Speed VLSI Interconnections was first published, several major developments have taken place in the field. Now, updated to reflect these advancements, this Second Edition includes new information on copper interconnections, nanotechnology circuit interconnects, electromigration in the copper interconnections, parasitic inductances, and RLC models for comprehensive analysis of interconnection delays and crosstalk.
Each chapter is designed to exist independently or as a part of one coherent unit, and several appropriate exercises are provided at the end of each chapter, challenging the reader to gain further insight into the contents being discussed. Chapter subjects include:
- Preliminary Concepts
- Parasitic Resistances, Capacitances, and Inductances
- Interconnection Delays
- Crosstalk Analysis
- Electromigration-Induced Failure Analysis
- Future Interconnections
High-Speed VLSI Interconnections, Second Edition is an indispensable reference for high-speed VLSI designers, RF circuit designers, and advanced students of electrical engineering.
About the Author
AShok k. Goel, PhD, is Associate Professor of Electrical Engineering at Michigan Technological University. He is the author of more than thirty journal publications and numerous conference proceedings. His research interests include nanotechnology circuit design, high-speed VLSI interconnections, device physics and modelling, and semiconductor TCAD.
1. Preliminary Concepts and More.
2. Parasitic Resistances, Capacitances and Inductances.
3. Interconnection Delays.
4. Crosstalk Analysis.
5. Electromigration-Induced Failure Analysis.
6. Future Interconnections.
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