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Home > Nanotechnology Columns > UAlbany College of Nanoscale Science and Engineering > CMOS-Nano Hybrid Research of CNSE NanoDesign and Modeling Group
Assistant Professor and Senior Research Scientist of Nanoscale Engineering
UAlbany- College of Nanoscale Science & Engineering
The marriage of nanotechnology and CMOS technology will lead to CMOS-nano hybrid technology, which can dramatically advance the development of future integrated circuits (ICs). The CNSE NanoDesign and Modeling (NDM) Group has made new progress in developing CMOS-nano hybrid technologies including the development of new interconnect-based CMOS-hybrid circuits and new reconfigurable structures utilizing nanojunction devices. These new methods open new opportunities to build next generation ICs and are expected to have a huge impact to world-wide IC industries.
July 25th, 2008
CMOS-Nano Hybrid Research of CNSE NanoDesign and Modeling Group
The future of the hundred-billion dollar semiconductor industry relies on the development of novel nanoelectronic devices, circuits and design approaches. Instead of completely replacing CMOS technology, non-conventional nanotechnology is expected to be hybrid with the CMOS systems. Such CMOS-nano hybrid systems try to utilize the advantages of both traditional CMOS devices and novel nanowire/nanotubes materials, which will enhance IC performances in the near future, and create breakthroughs in the long run.
The CNSE NanoDesign and Modeling (NDM) Group has carried out pioneer research in developing new CMOS-nano hybrid technologies. The new results are in two directions:
• Development of CMOS-nano hybrid circuits using new nanointerconnect structures
• Building CMOS-nano hybrid reconfigurable structures based on nanojunction devices
Development of CMOS-nano hybrid circuits using new nanointerconnect structures
The move towards nanoscale ICs poses new challenges to on-chip interconnect design. The currently used Cu interconnect is highly susceptible to electro-migration at high current densities and have low reliability in operation. The resistivity of Cu increases with a decrease in dimensions due to electron surface scattering and grain boundary scattering, which leads to a large interconnect delay and a low current density. Therefore, innovative interconnect materials are being extensively studied as next-generation interconnects.
|Figure 1: Proposed CMOS-nano IC utilizing carbon nanotubes and graphenes as interconnects.|
|Figure 2: Proposed CMOS-nano FPGA utilizing nanojunction devices.|